0
Index of /configAHR/Jump/0-coastlinecompg/FSS-OZR/root/sys/devices/system/cpu/cpu0/node0/memory46/power
Index of /configAHR/Jump/0-coastlinecompg/FSS-OZR/root/sys/devices/system/cpu/cpu0/node0/memory46/power
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h QEMU0002:00
h device:02
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B /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
#ifndef MLX5_MACSEC_H
#define MLX5_MACSEC_H
#ifdef CONFIG_MLX5_MACSEC
struct mlx5_macsec_event_data {
struct mlx5_macsec_fs *macsec_fs;
void *macdev;
u32 fs_id;
bool is_tx;
};
int mlx5_macsec_add_roce_rule(void *macdev, const struct sockaddr *addr, u16 gid_idx,
struct list_head *tx_rules_list, struct list_head *rx_rules_list,
struct mlx5_macsec_fs *macsec_fs);
void mlx5_macsec_del_roce_rule(u16 gid_idx, struct mlx5_macsec_fs *macsec_fs,
struct list_head *tx_rules_list, struct list_head *rx_rules_list);
void mlx5_macsec_add_roce_sa_rules(u32 fs_id, const struct sockaddr *addr, u16 gid_idx,
struct list_head *tx_rules_list,
struct list_head *rx_rules_list,
struct mlx5_macsec_fs *macsec_fs, bool is_tx);
void mlx5_macsec_del_roce_sa_rules(u32 fs_id, struct mlx5_macsec_fs *macsec_fs,
struct list_head *tx_rules_list,
struct list_head *rx_rules_list, bool is_tx);
#endif
#endif /* MLX5_MACSEC_H */
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Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/proc/thread-self/cwd/lib/python3.9/site-packages/tracer/controllers
Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/proc/thread-self/cwd/lib/python3.9/site-packages/tracer/controllers