ˆÃ „Î<ïÁÀ¿?÷/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright(c) 2016 - 2020 Intel Corporation. */ #ifndef DEF_RDMAVT_INCQP_H #define DEF_RDMAVT_INCQP_H #include #include #include #include #include /* * Atomic bit definitions for r_aflags. */ #define RVT_R_WRID_VALID 0 #define RVT_R_REWIND_SGE 1 /* * Bit definitions for r_flags. */ #define RVT_R_REUSE_SGE 0x01 #define RVT_R_RDMAR_SEQ 0x02 #define RVT_R_RSP_NAK 0x04 #define RVT_R_RSP_SEND 0x08 #define RVT_R_COMM_EST 0x10 /* * If a packet's QP[23:16] bits match this value, then it is * a PSM packet and the hardware will expect a KDETH header * following the BTH. */ #define RVT_KDETH_QP_PREFIX 0x80 #define RVT_KDETH_QP_SUFFIX 0xffff #define RVT_KDETH_QP_PREFIX_MASK 0x00ff0000 #define RVT_KDETH_QP_PREFIX_SHIFT 16 #define RVT_KDETH_QP_BASE (u32)(RVT_KDETH_QP_PREFIX << \ RVT_KDETH_QP_PREFIX_SHIFT) #define RVT_KDETH_QP_MAX (u32)(RVT_KDETH_QP_BASE + RVT_KDETH_QP_SUFFIX) /* * If a packet's LNH == BTH and DEST QPN[23:16] in the BTH match this * prefix value, then it is an AIP packet with a DETH containing the entropy * value in byte 4 following the BTH. */ #define RVT_AIP_QP_PREFIX 0x81 #define RVT_AIP_QP_SUFFIX 0xffff #define RVT_AIP_QP_PREFIX_MASK 0x00ff0000 #define RVT_AIP_QP_PREFIX_SHIFT 16 #define RVT_AIP_QP_BASE (u32)(RVT_AIP_QP_PREFIX << \ RVT_AIP_QP_PREFIX_SHIFT) #define RVT_AIP_QPN_MAX BIT(RVT_AIP_QP_PREFIX_SHIFT) #define RVT_AIP_QP_MAX (u32)(RVT_AIP_QP_BASE + RVT_AIP_QPN_MAX - 1) /* * Bit definitions for s_flags. * * RVT_S_SIGNAL_REQ_WR - set if QP send WRs contain completion signaled * RVT_S_BUSY - send tasklet is processing the QP * RVT_S_TIMER - the RC retry timer is active * RVT_S_ACK_PENDING - an ACK is waiting to be sent after RDMA read/atomics * RVT_S_WAIT_FENCE - waiting for all prior RDMA read or atomic SWQEs * before processing the next SWQE * RVT_S_WAIT_RDMAR - waiting for a RDMA read or atomic SWQE to complete * before processing the next SWQE * RVT_S_WAIT_RNR - waiting for RNR timeout * RVT_S_WAIT_SSN_CREDIT - waiting for RC credits to process next SWQE * RVT_S_WAIT_DMA - waiting for send DMA queue to drain before generating * next send completion entry not via send DMA * RVT_S_WAIT_PIO - waiting for a send buffer to be available * RVT_S_WAIT_TX - waiting for a struct verbs_txreq to be available * RVT_S_WAIT_DMA_DESC - waiting for DMA descriptors to be available * RVT_S_WAIT_KMEM - waiting for kernel memory to be available * RVT_S_WAIT_PSN - waiting for a packet to exit the send DMA queue * RVT_S_WAIT_ACK - waiting for an ACK packet before sending more requests * RVT_S_SEND_ONE - send one packet, request ACK, then wait for ACK * RVT_S_ECN - a BECN was queued to the send engine * RVT_S_MAX_BIT_MASK - The max bit that can be used by rdmavt */ #define RVT_S_SIGNAL_REQ_WR 0x0001 #define RVT_S_BUSY 0x0002 #define RVT_S_TIMER 0x0004 #define RVT_S_RESP_PENDING 0x0008 #define RVT_S_ACK_PENDING 0x0010 #define RVT_S_WAIT_FENCE 0x0020 #define RVT_S_WAIT_RDMAR 0x0040 #define RVT_S_WAIT_RNR 0x0080 #define RVT_S_WAIT_SSN_CREDIT 0x0100 #define RVT_S_WAIT_DMA 0x0200 #define RVT_S_WAIT_PIO 0x0400 #define RVT_S_WAIT_TX 0x0800 #define RVT_S_WAIT_DMA_DESC 0x1000 #define RVT_S_WAIT_KMEM 0x2000 #define RVT_S_WAIT_PSN 0x4000 #define RVT_S_WAIT_ACK 0x8000 #define RVT_S_SEND_ONE 0x10000 #define RVT_S_UNLIMITED_CREDIT 0x20000 #define RVT_S_ECN 0x40000 #define RVT_S_MAX_BIT_MASK 0x800000 /* * Drivers should use s_flags starting with bit 31 down to the bit next to * RVT_S_MAX_BIT_MASK */ /* * Wait flags that would prevent any packet type from being sent. */ #define RVT_S_ANY_WAIT_IO \ (RVT_S_WAIT_PIO | RVT_S_WAIT_TX | \ RVT_S_WAIT_DMA_DESC | RVT_S_WAIT_KMEM) /* * Wait flags that would prevent send work requests from making progress