1 ˆÃ 341Á¾ÄU/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* Copyright (c) 2018 Microsemi Corporation */ #ifndef __PHY_OCELOT_SERDES_H__ #define __PHY_OCELOT_SERDES_H__ #define SERDES1G(x) (x) #define SERDES1G_MAX SERDES1G(5) #define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) #define SERDES6G_MAX SERDES6G(2) #define SERDES_MAX (SERDES6G_MAX + 1) #endif ˆÃ ƒÁ¾Ä8/* SPDX-License-Identifier: GPL-2.0+ * * Copyright (C) 2016 Cogent Embedded Inc. */ #ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ #include /* r8a7745 CPG Core Clocks */ #define R8A7745_CLK_Z2 0 #define R8A7745_CLK_ZG 1 #define R8A7745_CLK_ZTR 2 #define R8A7745_CLK_ZTRD2 3 #define R8A7745_CLK_ZT 4 #define R8A7745_CLK_ZX 5 #define R8A7745_CLK_ZS 6 #define R8A7745_CLK_HP 7 #define R8A7745_CLK_B 9 #define R8A7745_CLK_LB 10 #define R8A7745_CLK_P 11 #define R8A7745_CLK_CL 12 #define R8A7745_CLK_CP 13 #define R8A7745_CLK_M2 14 #define R8A7745_CLK_ZB3 16 #define R8A7745_CLK_ZB3D2 17 #define R8A7745_CLK_DDR 18 #define R8A7745_CLK_SDH 19 #define R8A7745_CLK_SD0 20 #define R8A7745_CLK_SD2 21 #define R8A7745_CLK_SD3 22 #define R8A7745_CLK_MMC0 23 #define R8A7745_CLK_MP 24 #define R8A7745_CLK_QSPI 25 #define R8A7745_CLK_CPEX 26 #define R8A7745_CLK_RCAN 27 #define R8A7745_CLK_R 28 #define R8A7745_CLK_OSC 29 #endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */ ˆ ƒïÀ¾Äï Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/module/tpm/parameters

Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/module/tpm/parameters

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 suspend_pcr 2026-10-13 03:22 4.0K 
ˆ ƒ ,·À¾Ä7 Index of /configAHR/Jump/0-coastlinecompg/FSS-OZR/root/sys/module/tpm_tis

Index of /configAHR/Jump/0-coastlinecompg/FSS-OZR/root/sys/module/tpm_tis

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 parameters/ 2026-10-13 03:25 -  
ˆ ƒDÏÀ¾Äc Index of /FSS-OZR/root/proc/3106109/task/3106110/net/rpc