0 ˆÂÇ „lA|_Á¿Å?÷/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright © 2000-2010 David Woodhouse * Steven J. Hill * Thomas Gleixner * * Info: * Contains standard defines and IDs for NAND flash devices * * Changelog: * See git changelog. */ #ifndef __LINUX_MTD_RAWNAND_H #define __LINUX_MTD_RAWNAND_H #include #include #include #include #include #include #include #include #include struct nand_chip; struct gpio_desc; /* The maximum number of NAND chips in an array */ #define NAND_MAX_CHIPS 8 /* * Constants for hardware specific CLE/ALE/NCE function * * These are bits which can be or'ed to set/clear multiple * bits in one go. */ /* Select the chip by setting nCE to low */ #define NAND_NCE 0x01 /* Select the command latch by setting CLE to high */ #define NAND_CLE 0x02 /* Select the address latch by setting ALE to high */ #define NAND_ALE 0x04 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) #define NAND_CTRL_CHANGE 0x80 /* * Standard NAND flash commands */ #define NAND_CMD_READ0 0 #define NAND_CMD_READ1 1 #define NAND_CMD_RNDOUT 5 #define NAND_CMD_PAGEPROG 0x10 #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 #define NAND_CMD_SEQIN 0x80 #define NAND_CMD_RNDIN 0x85 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_PARAM 0xec #define NAND_CMD_GET_FEATURES 0xee #define NAND_CMD_SET_FEATURES 0xef #define NAND_CMD_RESET 0xff /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 #define NAND_CMD_RNDOUTSTART 0xE0 #define NAND_CMD_CACHEDPROG 0x15 #define NAND_CMD_NONE -1 /* Status bits */ #define NAND_STATUS_FAIL 0x01 #define NAND_STATUS_FAIL_N1 0x02 #define NAND_STATUS_TRUE_READY 0x20 #define NAND_STATUS_READY 0x40 #define NAND_STATUS_WP 0x80 #define NAND_DATA_IFACE_CHECK_ONLY -1 /* * Constants for Hardware ECC */ /* Reset Hardware ECC for read */ #define NAND_ECC_READ 0 /* Reset Hardware ECC for write */ #define NAND_ECC_WRITE 1 /* Enable Hardware ECC before syndrome is read back from flash */ #define NAND_ECC_READSYN 2 /* * Enable generic NAND 'page erased' check. This check is only done when * ecc.correct() returns -EBADMSG. * Set this flag if your implementation does not fix bitflips in erased * pages and you want to rely on the default implementation. */ #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) /* * Option constants for bizarre disfunctionality and real * features. */ /* Buswidth is 16 bit */ #define NAND_BUSWIDTH_16 BIT(1) /* * When using software implementation of Hamming, we can specify which byte * ordering should be used. */ #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) /* Chip has cache program function */ #define NAND_CACHEPRG BIT(3) /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG /* * Chip requires ready check on read (for auto-incremented sequential read). * True only for small page devices; large page devices do not support * autoincrement. */ #define NAND_NEED_READRDY BIT(8) /* Chip does not allow subpage writes */ #define NAND_NO_SUBPAGE_WRITE BIT(9) /* Device is one of 'new' xD cards that expose fake nand command set */ #define NAND_BROKEN_XD BIT(10) /* Device behaves just like nand, but is readonly */ #define NAND_ROM BIT(11) /* Device supports subpage reads */ #define NAND_SUBPAGE_READ BIT(12) /* Macros to identify the above */ #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) /* * Some MLC NANDs need data scrambling to limit bitflips caused by repeated * patterns. */ #define NAND_NEED_SCRAMBLING BIT(13) /* Device needs 3rd row address cycle */ #define NAND_ROW_ADDR_3 BIT(14) /* Non chip related options */ /* This option skips the bbt scan