PCI-MSIX-0000:00:02.0 *l4( (  fB- B_I|+Y/* SPDX-License-Identifier: GPL-2.0 */ /* Common header for intel-gtt.ko and i915.ko */ #ifndef _DRM_INTEL_GTT_H #define _DRM_INTEL_GTT_H #include struct agp_bridge_data; struct pci_dev; struct sg_table; void intel_gmch_gtt_get(u64 *gtt_total, phys_addr_t *mappable_base, resource_size_t *mappable_end); int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, struct agp_bridge_data *bridge); void intel_gmch_remove(void); bool intel_gmch_enable_gtt(void); void intel_gmch_gtt_flush(void); void intel_gmch_gtt_insert_page(dma_addr_t addr, unsigned int pg, unsigned int flags); void intel_gmch_gtt_insert_sg_entries(struct sg_table *st, unsigned int pg_start, unsigned int flags); void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); dma_addr_t intel_gmch_gtt_read_entry(unsigned int pg, bool *is_present, bool *is_local); /* Special gtt memory types */ #define AGP_DCACHE_MEMORY 1 #define AGP_PHYS_MEMORY 2 /* flag for GFDT type */ #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) #endif File not found.  0  0! am_J*j"TƞTţ{ Index of /anon_sym/anon/sys/dev/char/13:70/subsystem/input0/event0

Index of /anon_sym/anon/sys/dev/char/13:70/subsystem/input0/event0

 NameLast modifiedSizeDescription
 Parent Directory   -  
 subsystem/ 2026-10-11 12:29 -  
 device/ 2026-10-11 16:07 -  
 dev 2026-10-11 16:45 4.0K 
 power/ 2026-10-11 16:45 -  
 uevent 2026-10-11 16:45 4.0K 
 Y|_,/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2003 Russell King, All Rights Reserved. * * This driver supports the following PXA CPU/SSP ports:- * * PXA250 SSP * PXA255 SSP, NSSP * PXA26x SSP, NSSP, ASSP * PXA27x SSP1, SSP2, SSP3 * PXA3xx SSP1, SSP2, SSP3, SSP4 */ #ifndef __LINUX_PXA2XX_SSP_H #define __LINUX_PXA2XX_SSP_H #include #include #include #include #include #include struct clk; struct device; struct device_node; /* * SSP Serial Port Registers * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. * PXA255, PXA26x and PXA27x have extra ports, registers and bits. */ #define SSCR0 (0x00) /* SSP Control Register 0 */ #define SSCR1 (0x04) /* SSP Control Register 1 */ #define SSSR (0x08) /* SSP Status Register */ #define SSITR (0x0C) /* SSP Interrupt Test Register */ #define SSDR (0x10) /* SSP Data Write/Data Read Register */ #define SSTO (0x28)