1843200   D /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2019 Sean Anderson * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ #ifndef RESET_K210_SYSCTL_H #define RESET_K210_SYSCTL_H /* * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. * Taken from Kendryte SDK (kendryte-standalone-sdk). */ #define K210_RST_ROM 0 #define K210_RST_DMA 1 #define K210_RST_AI 2 #define K210_RST_DVP 3 #define K210_RST_FFT 4 #define K210_RST_GPIO 5 #define K210_RST_SPI0 6 #define K210_RST_SPI1 7 #define K210_RST_SPI2 8 #define K210_RST_SPI3 9 #define K210_RST_I2S0 10 #define K210_RST_I2S1 11 #define K210_RST_I2S2 12 #define K210_RST_I2C0 13 #define K210_RST_I2C1 14 #define K210_RST_I2C2 15 #define K210_RST_UART1 16 #define K210_RST_UART2 17 #define K210_RST_UART3 18 #define K210_RST_AES 19 #define K210_RST_FPIOA 20 #define K210_RST_TIMER0 21 #define K210_RST_TIMER1 22 #define K210_RST_TIMER2 23 #define K210_RST_WDT0 24 #define K210_RST_WDT1 25 #define K210_RST_SHA 26 #define K210_RST_RTC 29 #endif /* RESET_K210_SYSCTL_H */ !  OazD +jS Index of /anon_sym/anon/sys/devices/virtual/tty/tty4/subsystem/tty31

Index of /anon_sym/anon/sys/devices/virtual/tty/tty4/subsystem/tty31

 NameLast modifiedSizeDescription
 Parent Directory   -  
 dev 2026-10-12 18:14 4.0K 
 power/ 2026-10-12 18:14 -  
 subsystem/ 2026-10-11 21:02 -  
 uevent 2026-10-12 18:14 4.0K 
  }þ$ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2013 Samsung Electronics Co., Ltd. */ #ifndef _UNIPRO_H_ #define _UNIPRO_H_ /* * M-TX Configuration Attributes */ #define TX_HIBERN8TIME_CAPABILITY 0x000F #define TX_MODE 0x0021 #define TX_HSRATE_SERIES 0x0022 #define TX_HSGEAR 0x0023 #define TX_PWMGEAR 0x0024 #define TX_AMPLITUDE 0x0025 #define TX_HS_SLEWRATE 0x0026 #define TX_SYNC_SOURCE 0x0027 #define TX_HS_SYNC_LENGTH 0x0028 #define TX_HS_PREPARE_LENGTH 0x0029 #define TX_LS_PREPARE_LENGTH 0x002A #define TX_HIBERN8_CONTROL 0x002B #define TX_LCC_ENABLE 0x002C #define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D #define TX_BYPASS_8B10B_ENABLE 0x002E #define TX_DRIVER_POLARITY 0x002F #define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 #define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 #define TX_LCC_SEQUENCER 0x0032 #define TX_MIN_ACTIVATETIME 0x0033 #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 #define TX_REFCLKFREQ 0x00EB #define TX_CFGCLKFREQVAL 0x00EC #define CFGEXTRATTR 0x00F0 #define DITHERCTRL2 0x00F1 /* * M-RX Configuration Attributes */ #define RX_HS_G1_SYNC_LENGTH_CAP 0x008B #define RX_HS_G1_PREP_LENGTH_CAP 0x008C #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F #define RX_HIBERN8TIME_CAPABILITY 0x0092 #define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 #define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 #define RX_HS_