MAJOR=4 MINOR=48 DEVNAME=tty48 *l4( (  fB- y_I|+ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Unisoc SC9863A platform clocks * * Copyright (C) 2019, Unisoc Communications Inc. */ #ifndef _DT_BINDINGS_CLK_SC9863A_H_ #define _DT_BINDINGS_CLK_SC9863A_H_ #define CLK_MPLL0_GATE 0 #define CLK_DPLL0_GATE 1 #define CLK_LPLL_GATE 2 #define CLK_GPLL_GATE 3 #define CLK_DPLL1_GATE 4 #define CLK_MPLL1_GATE 5 #define CLK_MPLL2_GATE 6 #define CLK_ISPPLL_GATE 7 #define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1) #define CLK_AUDIO_GATE 0 #define CLK_RPLL 1 #define CLK_RPLL_390M 2 #define CLK_RPLL_260M 3 #define CLK_RPLL_195M 4 #define CLK_RPLL_26M 5 #define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1) #define CLK_TWPLL 0 #define CLK_TWPLL_768M 1 #define CLK_TWPLL_384M 2 #define CLK_TWPLL_192M 3 #define CLK_TWPLL_96M 4 #define CLK_TWPLL_48M 5 #define CLK_TWPLL_24M 6 #define CLK_TWPLL_12M 7 #define CLK_TWPLL_512M 8 #define CLK_TWPLL_256M 9 #define CLK_TWPLL_128M 10 #define CLK_TWPLL_64M 11 #define CLK_TWPLL_307M2 12 #define CLK_TWPLL_219M4 13 #define CLK_TWPLL_170M6 14 #define CLK_TWPLL_153M6 15 #define CLK_TWPLL_76M8 16 #define CLK_TWPLL_51M2 17 #define CLK_TWPLL_38M4 18 #define CLK_TWPLL_19M2 19 #define CLK_LPLL 20 #define CLK_LPLL_409M6 21 #define CLK_LPLL_245M76 22 #define CLK_GPLL 23 #define CLK_ISPPLL 24 #define CLK_ISPPLL_468M 25 #define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1) #define CLK_DPLL0 0 #define CLK_DPLL1 1 #define CLK_DPLL0_933M 2 #define CLK_DPLL0_622M3 3 #define CLK_DPLL0_400M 4 #define CLK_DPLL0_266M7 5 #define CLK_DPLL0_123M1 6 #define CLK_DPLL0_50M 7 #define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1) #define CLK_MPLL0 0 #define CLK_MPLL1 1 #define CLK_MPLL2 2 #define CLK_MPLL2_675M 3 #define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1) #define CLK_AP_APB 0 #define CLK_AP_CE 1 #define CLK_NANDC_ECC 2 #define CLK_NANDC_26M 3 #define CLK_EMMC_32K 4 #define CLK_SDIO0_32K 5 #define CLK_SDIO1_32K 6 #define CLK_SDIO2_32K 7 #define CLK_OTG_UTMI 8 #define CLK_AP_UART0 9 #define CLK_AP_UART1 10 #define CLK_AP_UART2 11 #define CLK_AP_UART3 12 #define CLK_AP_UART4 13 #define CLK_AP_I2C0 14 #define CLK_AP_I2C1 15 #define CLK_AP_I2C2 16 #define CLK_AP_I2C3 17 #define CLK_AP_I2C4 18 #define CLK_AP_I2C5 19 #define CLK_AP_I2C6 20 #define CLK_AP_SPI0 21 #define CLK_AP_SPI1 22 #define CLK_AP_SPI2 23 #define CLK_AP_SPI3 24 #define CLK_AP_IIS0 25 #define CLK_AP_IIS1 26 #define CLK_AP_IIS2 27 #define CLK_SIM0 28 #define CLK_SIM0_32K 29 #define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1) #define CLK_13M 0 #define CLK_6M5 1 #define CLK_4M3 2 #define CLK_2M 3 #define CLK_250K 4 #define CLK_RCO_25M 5 #define CLK_RCO_4M 6 #define CLK_RCO_2M 7 #define CLK_EMC 8 #define CLK_AON_APB 9 #define CLK_ADI 10 #define CLK_AUX0 11 #define CLK_AUX1 12 #define CLK_AUX2 13 #define CLK_PROBE 14 #define CLK_PWM0 15 #define CLK_PWM1 16 #define CLK_PWM2 17 #define CLK_AON_THM 18 #define CLK_AUDIF 19 #define CLK_CPU_DAP 20 #define CLK_CPU_TS 21 #define CLK_DJTAG_TCK 22 #define CLK_EMC_REF 23 #define CLK_CSSYS 24 #define CLK_AON_PMU 25 #define CLK_PMU_26M 26 #define CLK_AON_TMR 27 #define CLK_POWER_CPU 28 #define CLK_AP_AXI 29 #define CLK_SDIO0_2X 30 #define CLK_SDIO1_2X 31 #define CLK_SDIO2_2X 32 #define CLK_EMMC_2X 33 #define CLK_DPU 34 #define CLK_DPU_DPI 35 #define CLK_OTG_REF 36 #define CLK_SDPHY_APB 37 #define CLK_ALG_IO_APB 38 #define CLK_GPU_CORE 39 #define CLK_GPU_SOC 40 #define CLK_MM_EMC 41 #define CLK_MM_AHB 42 #define CLK_BPC 43 #define CLK_DCAM_IF 44 #define CLK_ISP 45 #define CLK_JPG 46 #define CLK_CPP 47 #define CLK_SENSOR0 48 #define CLK_SENSOR1 49 #define CLK_SENSOR2 50 #define CLK_MM_VEMC 51 #define CLK_MM_VAHB 52 #define CLK_VSP 53 #define CLK_CORE0 54 #define CLK_CORE1 55 #define CLK_CORE2 56 #define CLK_CORE3 57 #define CLK_CORE4 58 #define CLK_CORE5 59 #define CLK_CORE6 60 #define CLK_CORE7 61 #define CLK_SCU 62 #define CLK_ACE 63 #define CLK_AXI_PERIP