0 ˆÂÁ ƒ}×YÀ¾Ã&-/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOUND_AK4114_H #define __SOUND_AK4114_H /* * Routines for Asahi Kasei AK4114 * Copyright (c) by Jaroslav Kysela , */ /* AK4114 registers */ #define AK4114_REG_PWRDN 0x00 /* power down */ #define AK4114_REG_FORMAT 0x01 /* format control */ #define AK4114_REG_IO0 0x02 /* input/output control */ #define AK4114_REG_IO1 0x03 /* input/output control */ #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */ #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */ #define AK4114_REG_RCS0 0x06 /* receiver status 0 */ #define AK4114_REG_RCS1 0x07 /* receiver status 1 */ #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */ #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */ #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */ #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */ #define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */ #define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */ #define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */ #define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */ #define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */ #define AK4114_REG_TXCSB4 0x11 /* TX channel status byte 4 */ #define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */ #define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */ #define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */ #define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */ #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */ #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */ #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */ #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */ #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */ #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */ #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */ #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */ #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */ #define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */ /* sizes */ #define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1) #define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1) #define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1) /* AK4117_REG_PWRDN bits */ #define AK4114_CS12 (1<<7) /* Channel Status Select */ #define AK4114_BCU (1<<6) /* Block Start & C/U Output Mode */ #define AK4114_CM1 (1<<5) /* Master Clock Operation Select */ #define AK4114_CM0 (1<<4) /* Master Clock Operation Select */ #define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */ #define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */ #define AK4114_PWN (1<<1) /* 0 = power down, 1 = normal operation */ #define AK4114_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */ /* AK4114_REQ_FORMAT bits */ #define AK4114_MONO (1<<7) /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */ #define AK4114_DIF2 (1<<6) /* Audio Data Control */ #define AK4114_DIF1 (1<<5) /* Audio Data Control */ #define AK4114_DIF0 (1<<4) /* Audio Data Control */ #define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */ #define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */ #define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */ #define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */ #define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */ #define AK4114_DIF_24I2S (AK4114_DIF2|AK4114_DIF0) /* STDO: I2S */ #define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ #define AK4114_DIF_I24I2S (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S; LRCLK, BICK = Input */ #define AK4114_DEAU (1<<3) /* Deemphasis Autodetect Enable (1 = enable) */ #define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */ #define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis