1 "l4( (  fD- 741# SPDX-License-Identifier: GPL-2.0-only # # IBM Coherent Accelerator (CXL) compatible devices # config CXL_BASE bool select PPC_COPRO_BASE select PPC_64S_HASH_MMU config CXL tristate "Support for IBM Coherent Accelerators (CXL)" depends on PPC_POWERNV && PCI_MSI && EEH select CXL_BASE default m help Select this option to enable driver support for IBM Coherent Accelerators (CXL). CXL is otherwise known as Coherent Accelerator Processor Interface (CAPI). CAPI allows accelerators in FPGAs to be coherently attached to a CPU via an MMU. This driver enables userspace programs to access these accelerators via /dev/cxl/afuM.N devices. CAPI adapters are found in POWER8 based systems. If unsure, say N. _I|Mjq؂File not found.  736_I|Mdv &K Index of /anon_sym/anon/etc/security/console.perms.d

Index of /anon_sym/anon/etc/security/console.perms.d

 NameLast modifiedSizeDescription
 Parent Directory   -  
 l=J 2BP@n1h 0   M Index of /anon_sym/anon/sys/dev/char/4:57/subsystem/tty24

Index of /anon_sym/anon/sys/dev/char/4:57/subsystem/tty24

 NameLast modifiedSizeDescription
 Parent Directory   -  
 power/ 2026-10-11 16:12 -  
 subsystem/ 2026-10-11 06:17 -  
 dev 2026-10-11 16:15 4.0K 
 uevent 2026-10-11 16:15 4.0K 
* l4( (  fB- _I|+ d /* SPDX-License-Identifier: GPL-2.0 */ #undef TRACE_SYSTEM #define TRACE_SYSTEM page_pool #if !defined(_TRACE_PAGE_POOL_H) || defined(TRACE_HEADER_MULTI_READ) #define _TRACE_PAGE_POOL_H #include #include #include #include TRACE_EVENT(page_pool_release, TP_PROTO(const struct page_pool *pool, s32 inflight, u32 hold, u32 release), TP_ARGS(pool, inflight, hold, release), TP_STRUCT__entry( __field(const struct page_pool *, pool) __field(s32, inflight) __field(u32, hold) __field(u32, release) __field(u64, cnt) ), TP_fast_assign( __entry->pool = pool; __entry->inflight = inflight; __entry->hold = hold; __entry->release = release; __entry->cnt = pool->destroy_cnt; ), TP_printk("page_pool=%p inflight=%d hold=%u release=%u cnt=%llu", __