0x2E8
;
934Ͽ ;
Index of /anon_sym/anon/proc/self/root/sys/class/pci_bus
Index of /anon_sym/anon/proc/self/root/sys/class/pci_bus
=
h =MAJOR=7
MINOR=133
DEVNAME=vcsa5
# ?
yazD ;pBS !^ ?/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOUND_AK4117_H
#define __SOUND_AK4117_H
/*
* Routines for Asahi Kasei AK4117
* Copyright (c) by Jaroslav Kysela ,
*/
#define AK4117_REG_PWRDN 0x00 /* power down */
#define AK4117_REG_CLOCK 0x01 /* clock control */
#define AK4117_REG_IO 0x02 /* input/output control */
#define AK4117_REG_INT0_MASK 0x03 /* interrupt0 mask */
#define AK4117_REG_INT1_MASK 0x04 /* interrupt1 mask */
#define AK4117_REG_RCS0 0x05 /* receiver status 0 */
#define AK4117_REG_RCS1 0x06 /* receiver status 1 */
#define AK4117_REG_RCS2 0x07 /* receiver status 2 */
#define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */
#define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
#define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */
#define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */
#define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */
#define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
#define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
#define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
#define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
#define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
#define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
#define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
#define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
#define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
#define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
#define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
#define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
#define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
#define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */
/* sizes */
#define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
#define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
/* AK4117_REG_PWRDN bits */
#define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */
#define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
#define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
#define AK4117_XTL_11_2896M (0)
#define AK4117_XTL_12_288M AK4117_XTL0
#define AK4117_XTL_24_576M AK4117_XTL1
#define AK4117_XTL_EXT (AK4117_XTL1|AK4117_XTL0)
#define AK4117_PWN (1<<1) /* 0 = power down, 1 = normal operation */
#define AK4117_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */
/* AK4117_REQ_CLOCK bits */
#define AK4117_LP (1<<7) /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
#define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */
#define AK4117_PKCS0 (1<<5)
#define AK4117_PKCS_512fs (0)
#define AK4117_PKCS_256fs AK4117_PKCS0
#define AK4117_PKCS_128fs AK4117_PKCS1
#define AK4117_DIV (1<<4) /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
#define AK411