0x3E8 *  5_I|+azD 9q)F4 /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (c) 2011 Samsung Electronics Co., Ltd * http://www.samsung.com */ #ifndef __LINUX_MFD_S5M8763_H #define __LINUX_MFD_S5M8763_H /* S5M8763 registers */ enum s5m8763_reg { S5M8763_REG_IRQ1, S5M8763_REG_IRQ2, S5M8763_REG_IRQ3, S5M8763_REG_IRQ4, S5M8763_REG_IRQM1, S5M8763_REG_IRQM2, S5M8763_REG_IRQM3, S5M8763_REG_IRQM4, S5M8763_REG_STATUS1, S5M8763_REG_STATUS2, S5M8763_REG_STATUSM1, S5M8763_REG_STATUSM2, S5M8763_REG_CHGR1, S5M8763_REG_CHGR2, S5M8763_REG_LDO_ACTIVE_DISCHARGE1, S5M8763_REG_LDO_ACTIVE_DISCHARGE2, S5M8763_REG_BUCK_ACTIVE_DISCHARGE3, S5M8763_REG_ONOFF1, S5M8763_REG_ONOFF2, S5M8763_REG_ONOFF3, S5M8763_REG_ONOFF4, S5M8763_REG_BUCK1_VOLTAGE1, S5M8763_REG_BUCK1_VOLTAGE2, S5M8763_REG_BUCK1_VOLTAGE3, S5M8763_REG_BUCK1_VOLTAGE4, S5M8763_REG_BUCK2_VOLTAGE1, S5M8763_REG_BUCK2_VOLTAGE2, S5M8763_REG_BUCK3, S5M8763_REG_BUCK4, S5M8763_REG_LDO1_LDO2, S5M8763_REG_LDO3, S5M8763_REG_LDO4, S5M8763_REG_LDO5, S5M8763_REG_LDO6, S5M8763_REG_LDO7, S5M8763_REG_LDO7_LDO8, S5M8763_REG_LDO9_LDO10, S5M8763_REG_LDO11, S5M8763_REG_LDO12, S5M8763_REG_LDO13, S5M8763_REG_LDO14, S5M8763_REG_LDO15, S5M8763_REG_LDO16, S5M8763_REG_BKCHR, S5M8763_REG_LBCNFG1, S5M8763_REG_LBCNFG2, }; /* S5M8763 regulator ids */ enum s5m8763_regulators { S5M8763_LDO1, S5M8763_LDO2, S5M8763_LDO3, S5M8763_LDO4, S5M8763_LDO5, S5M8763_LDO6, S5M8763_LDO7, S5M8763_LDO8, S5M8763_LDO9, S5M8763_LDO10, S5M8763_LDO11, S5M8763_LDO12, S5M8763_LDO13, S5M8763_LDO14, S5M8763_LDO15, S5M8763_LDO16, S5M8763_BUCK1, S5M8763_BUCK2, S5M8763_BUCK3, S5M8763_BUCK4, S5M8763_AP_EN32KHZ, S5M8763_CP_EN32KHZ, S5M8763_ENCHGVI, S5M8763_ESAFEUSB1, S5M8763_ESAFEUSB2, }; #define S5M8763_ENRAMP (1 << 4) #endif /* __LINUX_MFD_S5M8763_H */    /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ /* * This header provides constants for binding nvidia,tegra194-gpio*. * * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below * provide names for this. * * The second cell contains standard flag values specified in gpio.h. */ #ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H #define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H #include /* GPIOs implemented by main GPIO controller */ #define TEGRA194_MAIN_GPIO_PORT_A 0 #define TEGRA194_MAIN_GPIO_PORT_B 1 #define TEGRA194_MAIN_GPIO_PORT_C 2 #define TEGRA194_MAIN_GPIO_PORT_D 3 #define TEGRA194_MAIN_GPIO_PORT_E 4 #define TEGRA194_MAIN_GPIO_PORT_F 5 #define TEGRA194_MAIN_GPIO_PORT_G 6 #define TEGRA194_MAIN_GPIO_PORT_H 7 #define TEGRA194_MAIN_GPIO_PORT_I 8 #define TEGRA194_MAIN_GPIO_PORT_J 9 #define TEGRA194_MAIN_GPIO_PORT_K 10 #define TEGRA194_MAIN_GPIO_PORT_L 11 #define TEGRA194_MAIN_GPIO_PORT_M 12 #define TEGRA194_MAIN_GPIO_PORT_N 13 #define TEGRA194_MAIN_GPIO_PORT_O 14 #define TEGRA194_MAIN_GPIO_PORT_P 15 #define TEGRA194_MAIN_GPIO_PORT_Q 16 #define TEGRA194_MAIN_GPIO_PORT_R 17 #define TEGRA194_MAIN_GPIO_PORT_S 18 #define TEGRA194_MAIN_GPIO_PORT_T 19 #define TEGRA194_MAIN_GPIO_PORT_U 20 #define TEGRA194_MAIN_GPIO_PORT_V 21 #define TEGRA194_MAIN_GPIO_PORT_W 22 #define TEGRA194_MAIN_GPIO_PORT_X 23 #define TEGRA194_MAIN_GPIO_PORT_Y 24 #define TEGRA194_MAIN_GPIO_PORT_Z 25 #define TEGRA194_MAIN_GPIO_PORT_FF 26 #define TEGRA194_MAIN_GPIO_PORT_GG 27 #define TEGRA194_MAIN_GPIO(port, offset) \ ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) /* GPIOs implemented by AON GPIO controller */ #define TEGRA194_AON_GPIO_PORT_AA 0 #define TEGRA194_AON_GPIO_PORT_BB 1 #define TEGRA194_AON_GPIO_PORT_CC 2 #define TEGRA194_AON_GPIO_PORT_DD 3 #define TEGRA194_AON_GPIO_PORT_EE 4 #define TEGRA194_AON_GPIO(port, offset) \ ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) #endif  ¾ Index of /anon_sym/anon/proc/sel