disabled  N5_I|Mdv &K Index of /anon_sym/anon/sys/class/tty/tty26/subsystem/tty15

Index of /anon_sym/anon/sys/class/tty/tty26/subsystem/tty15

 NameLast modifiedSizeDescription
 Parent Directory   -  
 dev 2026-10-12 11:20 4.0K 
 power/ 2026-10-12 11:20 -  
 subsystem/ 2026-10-11 21:02 -  
 uevent 2026-10-12 11:20 4.0K 
 ; Index of /FSS-OZR/root/sys/bus/acpi/devices/LNXCPU:00/subsystem

Index of /FSS-OZR/root/sys/bus/acpi/devices/LNXCPU:00/subsystem

 NameLast modifiedSizeDescription
 Parent Directory   -  
 devices/ 2026-10-12 07:00 -  
 drivers/ 2026-10-12 11:19 -  
 drivers_autoprobe 2026-10-12 11:20 4.0K 
 drivers_probe 2026-10-12 11:20 4.0K 
 uevent 2026-10-12 11:20 4.0K 
*l4( (  fB- _I|+/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ /* * This header provides constants for binding nvidia,tegra234-gpio*. * * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below * provide names for this. * * The second cell contains standard flag values specified in gpio.h. */ #ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H #define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H #include /* GPIOs implemented by main GPIO controller */ #define TEGRA234_MAIN_GPIO_PORT_A 0 #define TEGRA234_MAIN_GPIO_PORT_B 1 #define TEGRA234_MAIN_GPIO_PORT_C 2 #define TEGRA234_MAIN_GPIO_PORT_D 3 #define TEGRA234_MAIN_GPIO_PORT_E 4 #define TEGRA234_MAIN_GPIO_PORT_F 5 #define TEGRA234_MAIN_GPIO_PORT_G 6 #define TEGRA234_MA