MAJOR=4 MINOR=1 DEVNAME=tty1 KKFile not found. M 0 O i_?O/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H /** * @file * @defgroup bpmp_clock_ids Clock ID's * @{ */ /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */ #define TEGRA234_CLK_ACTMON 1U /** @brief output of gate CLK_ENB_ADSP */ #define TEGRA234_CLK_ADSP 2U /** @brief output of gate CLK_ENB_ADSPNEON */ #define TEGRA234_CLK_ADSPNEON 3U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ #define TEGRA234_CLK_AHUB 4U /** @brief output of gate CLK_ENB_APB2APE */ #define TEGRA234_CLK_APB2APE 5U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ #define TEGRA234_CLK_APE 6U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ #define TEGRA234_CLK_AUD_MCLK 7U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ #define TEGRA234_CLK_AXI_CBB 8U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ #define TEGRA234_CLK_CAN1 9U /** @brief output of gate CLK_ENB_CAN1_HOST */ #define TEGRA234_CLK_CAN1_HOST 10U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ #define TEGRA234_CLK_CAN2 11U /** @brief output of gate CLK_ENB_CAN2_HOST */ #define TEGRA234_CLK_CAN2_HOST 12U /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ #define TEGRA234_CLK_CLK_M 14U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ #define TEGRA234_CLK_DMIC1 15U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ #define TEGRA234_CLK_DMIC2 16U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ #define TEGRA234_CLK_DMIC3 17U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ #define TEGRA234_CLK_DMIC4 18U /** @brief output of gate CLK_ENB_DPAUX */ #define TEGRA234_CLK_DPAUX 19U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */ #define TEGRA234_CLK_NVJPG1 20U /** * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY * divided by the divider controlled by ACLK_CLK_DIVISOR in * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ #define TEGRA234_CLK_ACLK 21U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */ #define TEGRA234_CLK_MSS_ENCRYPT 22U /** @brief clock recovered from EAVB input */ #define TEGRA234_CLK_EQOS_RX_INPUT 23U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */ #define TEGRA234_CLK_AON_APB 25U /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */ #define TEGRA234_CLK_AON_NIC 26U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */ #define TEGRA234_CLK_AON_CPU_NIC 27U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ #define TEGRA234_CLK_PLLA1 28U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ #define TEGRA234_CLK_DSPK1 29U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ #define TEGRA234_CLK_DSPK2 30U /** * @brief controls the EMC clock frequency. * @details Doing a clk_set_rate on this clock will select the * appropriate clock source, program the source rate and execute a * specific sequence to switch to the new clock source for both memory * controllers. This can be used to control the balance between memory * throughput and memory controller power. */ #define TEGRA234_CLK_EMC 31U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */ #define TEGRA234_CLK_EQOS_AXI 32U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */ #define TEGRA234_CLK_EQOS_PTP_REF 33U /** @brief output of gate CLK_ENB_EQOS_RX */ #define TEGRA234_CLK_EQOS_RX 34U /** @brief CLK_RST_CONTRO