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  *   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿÄƒ|,ƒ_†I|¥�+ÃÇ #ª    /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * Copyright(c) 2018 Intel Corporation
 */

#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__

#include <sound/sof/header.h>

/*
 * Component
 */

/* types of component */
enum sof_comp_type {
	SOF_COMP_NONE = 0,
	SOF_COMP_HOST,
	SOF_COMP_DAI,
	SOF_COMP_SG_HOST,	/**< scatter gather variant */
	SOF_COMP_SG_DAI,	/**< scatter gather variant */
	SOF_COMP_VOLUME,
	SOF_COMP_MIXER,
	SOF_COMP_MUX,
	SOF_COMP_SRC,
	SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */
	SOF_COMP_TONE,
	SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */
	SOF_COMP_BUFFER,
	SOF_COMP_EQ_IIR,
	SOF_COMP_EQ_FIR,
	SOF_COMP_KEYWORD_DETECT,
	SOF_COMP_KPB,			/* A key phrase buffer component */
	SOF_COMP_SELECTOR,		/**< channel selector component */
	SOF_COMP_DEMUX,
	SOF_COMP_ASRC,		/**< Asynchronous sample rate converter */
	SOF_COMP_DCBLOCK,
	SOF_COMP_SMART_AMP,             /**< smart amplifier component */
	SOF_COMP_MODULE_ADAPTER,		/**< module adapter */
	/* keep FILEREAD/FILEWRITE as the last ones */
	SOF_COMP_FILEREAD = 10000,	/**< host test based file IO */
	SOF_COMP_FILEWRITE = 10001,	/**< host test based file IO */
};

/* XRUN action for component */
#define SOF_XRUN_STOP		1	/**< stop stream */
#define SOF_XRUN_UNDER_ZERO	2	/**< send 0s to sink */
#define SOF_XRUN_OVER_NULL	4	/**< send data to NULL */

/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
struct sof_ipc_comp {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t id;
	uint32_t type;
	uint32_t pipeline_id;
	uint32_t core;

	/* extended data length, 0 if no extended data */
	uint32_t ext_data_length;
} __packed __aligned(4);

/*
 * Component Buffers
 */

/*
 * SOF memory capabilities, add new ones at the end
 */
#define SOF_MEM_CAPS_RAM		BIT(0)
#define SOF_MEM_CAPS_ROM		BIT(1)
#define SOF_MEM_CAPS_EXT		BIT(2) /**< external */
#define SOF_MEM_CAPS_LP			BIT(3) /**< low power */
#define SOF_MEM_CAPS_HP			BIT(4) /**< high performance */
#define SOF_MEM_CAPS_DMA		BIT(5) /**< DMA'able */
#define SOF_MEM_CAPS_CACHE		BIT(6) /**< cacheable */
#define SOF_MEM_CAPS_EXEC		BIT(7) /**< executable */
#define SOF_MEM_CAPS_L3			BIT(8) /**< L3 memory */

/*
 * overrun will cause ring buffer overwrite, instead of XRUN.
 */
#define SOF_BUF_OVERRUN_PERMITTED	BIT(0)

/*
 * underrun will cause readback of 0s, instead of XRUN.
 */
#define SOF_BUF_UNDERRUN_PERMITTED	BIT(1)

/* the UUID size in bytes, shared between FW and host */
#define SOF_UUID_SIZE	16

/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
struct sof_ipc_buffer {
	struct sof_ipc_comp comp;
	uint32_t size;		/**< buffer size in bytes */
	uint32_t caps;		/**< SOF_MEM_CAPS_ */
	uint32_t flags;		/**< SOF_BUF_ flags defined above */
	uint32_t reserved;	/**< reserved for future use */
} __packed __aligned(4);

/* generic component config data - must always be after struct sof_ipc_comp */
struct sof_ipc_comp_config {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t periods_sink;	/**< 0 means variable */
	uint32_t periods_source;/**< 0 means variable */
	uint32_t reserved1;	/**< reserved */
	uint32_t frame_fmt;	/**< SOF_IPC_FRAME_ */
	uint32_t xrun_action;

	/* reserved for future use */
	uint32_t reserved[2];
} __packed __aligned(4);

/* generic host component */
struct sof_ipc_comp_host {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	uint32_t direction;	/**< SOF_IPC_STREAM_ */
	uint32_t no_irq;	/**< don't send periodic IRQ to host/DSP */
	uint32_t dmac_config; /**< DMA engine specific */
} __packed __aligned(4);

/* generic DAI component */
struct sof_ipc_comp_dai {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	uint32_t direction;	/**< SOF_IPC_STREAM_ */
	uint32_t dai_index;	/**< index of this type dai */
	uint32_t type;		/**< DAI type - SOF_DAI_ */
	uint32_t 