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  *   1ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿÐƒí»_†I|¥�+ÂÎ ¥    1/* SPDX-License-Identifier: GPL-2.0 */
/*
 * STM32 Low-Power Timer parent driver.
 * Copyright (C) STMicroelectronics 2017
 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
 * Inspired by Benjamin Gaignard's stm32-timers driver
 */

#ifndef _LINUX_STM32_LPTIMER_H_
#define _LINUX_STM32_LPTIMER_H_

#include <linux/clk.h>
#include <linux/regmap.h>

#define STM32_LPTIM_ISR		0x00	/* Interrupt and Status Reg  */
#define STM32_LPTIM_ICR		0x04	/* Interrupt Clear Reg       */
#define STM32_LPTIM_IER		0x08	/* Interrupt Enable Reg      */
#define STM32_LPTIM_CFGR	0x0C	/* Configuration Reg         */
#define STM32_LPTIM_CR		0x10	/* Control Reg               */
#define STM32_LPTIM_CMP		0x14	/* Compare Reg               */
#define STM32_LPTIM_ARR		0x18	/* Autoreload Reg            */
#define STM32_LPTIM_CNT		0x1C	/* Counter Reg               */

/* STM32_LPTIM_ISR - bit fields */
#define STM32_LPTIM_CMPOK_ARROK		GENMASK(4, 3)
#define STM32_LPTIM_ARROK		BIT(4)
#define STM32_LPTIM_CMPOK		BIT(3)

/* STM32_LPTIM_ICR - bit fields */
#define STM32_LPTIM_ARRMCF		BIT(1)
#define STM32_LPTIM_CMPOKCF_ARROKCF	GENMASK(4, 3)

/* STM32_LPTIM_IER - bit flieds */
#define STM32_LPTIM_ARRMIE	BIT(1)

/* STM32_LPTIM_CR - bit fields */
#define STM32_LPTIM_CNTSTRT	BIT(2)
#define STM32_LPTIM_SNGSTRT	BIT(1)
#define STM32_LPTIM_ENABLE	BIT(0)

/* STM32_LPTIM_CFGR - bit fields */
#define STM32_LPTIM_ENC		BIT(24)
#define STM32_LPTIM_COUNTMODE	BIT(23)
#define STM32_LPTIM_WAVPOL	BIT(21)
#define STM32_LPTIM_PRESC	GENMASK(11, 9)
#define STM32_LPTIM_CKPOL	GENMASK(2, 1)

/* STM32_LPTIM_ARR */
#define STM32_LPTIM_MAX_ARR	0xFFFF

/**
 * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device
 * @clk: clock reference for this instance
 * @regmap: register map reference for this instance
 * @has_encoder: indicates this Low-Power Timer supports encoder mode
 */
struct stm32_lptimer {
	struct clk *clk;
	struct regmap *regmap;
	bool has_encoder;
};

#endif
     3ˆ¿Ñ„ži¿¾ÂÎ 2-    3/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * max77686-private.h - Voltage regulator driver for the Maxim 77686/802
 *
 *  Copyright (C) 2012 Samsung Electrnoics
 *  Chiwoong Byun <woong.byun@samsung.com>
 */

#ifndef __LINUX_MFD_MAX77686_PRIV_H
#define __LINUX_MFD_MAX77686_PRIV_H

#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/module.h>

#define MAX77686_REG_INVALID		(0xff)

/* MAX77686 PMIC registers */
enum max77686_pmic_reg {
	MAX77686_REG_DEVICE_ID		= 0x00,
	MAX77686_REG_INTSRC		= 0x01,
	MAX77686_REG_INT1		= 0x02,
	MAX77686_REG_INT2		= 0x03,

	MAX77686_REG_INT1MSK		= 0x04,
	MAX77686_REG_INT2MSK		= 0x05,

	MAX77686_REG_STATUS1		= 0x06,
	MAX77686_REG_STATUS2		= 0x07,

	MAX77686_REG_PWRON		= 0x08,
	MAX77686_REG_ONOFF_DELAY	= 0x09,
	MAX77686_REG_MRSTB		= 0x0A,
	/* Reserved: 0x0B-0x0F */

	MAX77686_REG_BUCK1CTRL		= 0x10,
	MAX77686_REG_BUCK1OUT		= 0x11,
	MAX77686_REG_BUCK2CTRL1		= 0x12,
	MAX77686_REG_BUCK234FREQ	= 0x13,
	MAX77686_REG_BUCK2DVS1		= 0x14,
	MAX77686_REG_BUCK2DVS2		= 0x15,
	MAX77686_REG_BUCK2DVS3		= 0x16,
	MAX77686_REG_BUCK2DVS4		= 0x17,
	MAX77686_REG_BUCK2DVS5		= 0x18,
	MAX77686_REG_BUCK2DVS6		= 0x19,
	MAX77686_REG_BUCK2DVS7		= 0x1A,
	MAX77686_REG_BUCK2DVS8		= 0x1B,
	MAX77686_REG_BUCK3CTRL1		= 0x1C,
	/* Reserved: 0x1D */
	MAX77686_REG_BUCK3DVS1		= 0x1E,
	MAX77686_REG_BUCK3DVS2		= 0x1F,
	MAX77686_REG_BUCK3DVS3		= 0x20,
	MAX77686_REG_BUCK3DVS4		= 0x21,
	MAX77686_REG_BUCK3DVS5		= 0x22,
	MAX77686_REG_BUCK3DVS6		= 0x23,
	MAX77686_REG_BUCK3DVS7		= 0x24,
	MAX77686_REG_BUCK3DVS8		= 0x25,
	MAX77686_REG_BUCK4CTRL1		= 0x26,
	/* Reserved: 0x27 */
	MAX77686_REG_BUCK4DVS1		= 0x28,
	MAX77686_REG_BUCK4DVS2		= 0x29,
	MAX77686_REG_BUCK4DVS3		= 0x2A,
	MAX77686_REG_BUCK4DVS4		= 0x2B,
	MAX77686_REG_BUCK4DVS5		= 0x2C,
	MAX77686_REG_BUCK4DVS6		= 0x2D,
	MAX77686_REG_BUCK4DVS7		= 0x2E,
	MAX77686_REG_BUCK4DVS8		= 0x2F,
	MAX77686_REG_BUCK5CTRL		= 0x30,
	MAX77686_REG_BUCK5OUT		= 0x31,
	MAX77686_R