MAJOR=4
MINOR=1
DEVNAME=tty1
  #   %ˆÀÎ654¿a–Ðz¾””ÔD¨ 	Å€nàSÿÑ Ž    %/* SPDX-License-Identifier: GPL-2.0 */
//
// ALSA SoC Texas Instruments TAS2770 Audio Smart Amplifier
//
// Copyright (C) 2025 Texas Instruments Incorporated
// https://www.ti.com
//
// The TAS2770 hda driver implements for one, two, or even multiple
// TAS2770 chips.
//
// Author: Baojun Xu <baojun.xu@ti.com>
//

#ifndef __TAS2770_TLV_H__
#define __TAS2770_TLV_H__

#define TAS2770_DVC_LEVEL		TASDEVICE_REG(0x0, 0x0, 0x05)
#define TAS2770_AMP_LEVEL		TASDEVICE_REG(0x0, 0x0, 0x03)

static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2770_dvc_tlv, -10000, 50, 0);
static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2770_amp_tlv, 1100, 50, 0);

#endif
     'ˆÁÏ„‚Ø?À¾Ñ /v    '/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 */

#ifndef _DT_BINDINGS_CLK_MT8183_H
#define _DT_BINDINGS_CLK_MT8183_H

/* APMIXED */
#define CLK_APMIXED_ARMPLL_LL		0
#define CLK_APMIXED_ARMPLL_L		1
#define CLK_APMIXED_CCIPLL		2
#define CLK_APMIXED_MAINPLL		3
#define CLK_APMIXED_UNIV2PLL		4
#define CLK_APMIXED_MSDCPLL		5
#define CLK_APMIXED_MMPLL		6
#define CLK_APMIXED_MFGPLL		7
#define CLK_APMIXED_TVDPLL		8
#define CLK_APMIXED_APLL1		9
#define CLK_APMIXED_APLL2		10
#define CLK_APMIXED_SSUSB_26M		11
#define CLK_APMIXED_APPLL_26M		12
#define CLK_APMIXED_MIPIC0_26M		13
#define CLK_APMIXED_MDPLLGP_26M		14
#define CLK_APMIXED_MMSYS_26M		15
#define CLK_APMIXED_UFS_26M		16
#define CLK_APMIXED_MIPIC1_26M		17
#define CLK_APMIXED_MEMPLL_26M		18
#define CLK_APMIXED_CLKSQ_LVPLL_26M	19
#define CLK_APMIXED_MIPID0_26M		20
#define CLK_APMIXED_MIPID1_26M		21
#define CLK_APMIXED_NR_CLK		22

/* TOPCKGEN */
#define CLK_TOP_MUX_AXI			0
#define CLK_TOP_MUX_MM			1
#define CLK_TOP_MUX_CAM			2
#define CLK_TOP_MUX_MFG			3
#define CLK_TOP_MUX_CAMTG		4
#define CLK_TOP_MUX_UART		5
#define CLK_TOP_MUX_SPI			6
#define CLK_TOP_MUX_MSDC50_0_HCLK	7
#define CLK_TOP_MUX_MSDC50_0		8
#define CLK_TOP_MUX_MSDC30_1		9
#define CLK_TOP_MUX_MSDC30_2		10
#define CLK_TOP_MUX_AUDIO		11
#define CLK_TOP_MUX_AUD_INTBUS		12
#define CLK_TOP_MUX_FPWRAP_ULPOSC	13
#define CLK_TOP_MUX_SCP			14
#define CLK_TOP_MUX_ATB			15
#define CLK_TOP_MUX_SSPM		16
#define CLK_TOP_MUX_DPI0		17
#define CLK_TOP_MUX_SCAM		18
#define CLK_TOP_MUX_AUD_1		19
#define CLK_TOP_MUX_AUD_2		20
#define CLK_TOP_MUX_DISP_PWM		21
#define CLK_TOP_MUX_SSUSB_TOP_XHCI	22
#define CLK_TOP_MUX_USB_TOP		23
#define CLK_TOP_MUX_SPM			24
#define CLK_TOP_MUX_I2C			25
#define CLK_TOP_MUX_F52M_MFG		26
#define CLK_TOP_MUX_SENINF		27
#define CLK_TOP_MUX_DXCC		28
#define CLK_TOP_MUX_CAMTG2		29
#define CLK_TOP_MUX_AUD_ENG1		30
#define CLK_TOP_MUX_AUD_ENG2		31
#define CLK_TOP_MUX_FAES_UFSFDE		32
#define CLK_TOP_MUX_FUFS		33
#define CLK_TOP_MUX_IMG			34
#define CLK_TOP_MUX_DSP			35
#define CLK_TOP_MUX_DSP1		36
#define CLK_TOP_MUX_DSP2		37
#define CLK_TOP_MUX_IPU_IF		38
#define CLK_TOP_MUX_CAMTG3		39
#define CLK_TOP_MUX_CAMTG4		40
#define CLK_TOP_MUX_PMICSPI		41
#define CLK_TOP_SYSPLL_CK		42
#define CLK_TOP_SYSPLL_D2		43
#define CLK_TOP_SYSPLL_D3		44
#define CLK_TOP_SYSPLL_D5		45
#define CLK_TOP_SYSPLL_D7		46
#define CLK_TOP_SYSPLL_D2_D2		47
#define CLK_TOP_SYSPLL_D2_D4		48
#define CLK_TOP_SYSPLL_D2_D8		49
#define CLK_TOP_SYSPLL_D2_D16		50
#define CLK_TOP_SYSPLL_D3_D2		51
#define CLK_TOP_SYSPLL_D3_D4		52
#define CLK_TOP_SYSPLL_D3_D8		53
#define CLK_TOP_SYSPLL_D5_D2		54
#define CLK_TOP_SYSPLL_D5_D4		55
#define CLK_TOP_SYSPLL_D7_D2		56
#define CLK_TOP_SYSPLL_D7_D4		57
#define CLK_TOP_UNIVPLL_CK		58
#define CLK_TOP_UNIVPLL_D2		59
#define CLK_TOP_UNIVPLL_D3		60
#define CLK_TOP_UNIVPLL_D5		61
#define CLK_TOP_UNIVPLL_D7		62
#define CLK_TOP_UNIVPLL_D2_D2		63
#define CLK_TOP_UNIVPLL_D2_D4		64
#define CLK_TOP_UNIVPLL_D2_D8		65
#define CLK_TOP_UNIVPLL_D3_D2		66
#define CLK_TOP_UNIVPLL_D3_D4		67
#define CLK_TOP_UNIVPLL_D3_D8		68
#define CLK_TOP_UNIVPLL_D5_D2		69
#define CLK_TOP_UNIVPLL_D5_D4		70
#define CLK_TOP_UNIVPLL_D5_D8		71
#define CLK_TOP_APLL1_CK		72
#define CLK_TOP_APLL1_D2		73
#define CLK_TOP_APLL1_D4