MAJOR=4 MINOR=44 DEVNAME=tty44   yƛ_I|+! /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for binding nvidia,tegra124-car or * nvidia,tegra132-car. * * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB * registers. These IDs often match those in the CAR's RST_DEVICES registers, * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In * this case, those clocks are assigned IDs above 185 in order to highlight * this issue. Implementations that interpret these clock IDs as bit values * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to * explicitly handle these special cases. * * The balance of the clocks controlled by the CAR are assigned IDs of 185 and * above. */ #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H /* 0 */ /* 1 */ /* 2 */ #define TEGRA124_CLK_ISPB 3 #define TEGRA124_CLK_RTC 4 #define TEGRA124_CLK_TIMER 5 #define TEGRA124_CLK_UARTA 6 /* 7 (register bit affects uartb and vfir) */ /* 8 */ #define TEGRA124_CLK_SDMMC2 9 /* 10 (register bit affects spdif_in and spdif_out) */ #define TEGRA124_CLK_I2S1 11 #define TEGRA124_CLK_I2C1 12 /* 13 */ #define TEGRA124_CLK_SDMMC1 14 #define TEGRA124_CLK_SDMMC4 15 /* 16 */ #define TEGRA124_CLK_PWM 17 #define TEGRA124_CLK_I2S2 18 /* 20 (register bit affects vi and vi_sensor) */ /* 21 */ #define TEGRA124_CLK_USBD 22 #define TEGRA124_CLK_ISP 23 /* 26 */ /* 25 */ #define TEGRA124_CLK_DISP2 26 #define TEGRA124_CLK_DISP1 27 #define TEGRA124_CLK_HOST1X 28 #define TEGRA124_CLK_VCP 29 #define TEGRA124_CLK_I2S0 30 /* 31 */ #define TEGRA124_CLK_MC 32 /* 33 */ #define TEGRA124_CLK_APBDMA 34 /* 35 */ #define TEGRA124_CLK_KBC 36 /* 37 */ /* 38 */ /* 39 (register bit affects fuse and fuse_burn) */ #define TEGRA124_CLK_KFUSE 40 #define TEGRA124_CLK_SBC1 41 #define TEGRA124_CLK_NOR 42 /* 43 */ #define TEGRA124_CLK_SBC2 44 /* 45 */ #define TEGRA124_CLK_SBC3 46 #define TEGRA124_CLK_I2C5 47 #define TEGRA124_CLK_DSIA 48 /* 49 */ #define TEGRA124_CLK_MIPI 50 #define TEGRA124_CLK_HDMI 51 #define TEGRA124_CLK_CSI 52 /* 53 */ #define TEGRA124_CLK_I2C2 54 #define TEGRA124_CLK_UARTC 55 #define TEGRA124_CLK_MIPI_CAL 56 #define TEGRA124_CLK_EMC 57 #define TEGRA124_CLK_USB2 58 #define TEGRA124_CLK_USB3 59 /* 60 */ #define TEGRA124_CLK_VDE 61 #define TEGRA124_CLK_BSEA 62 #define TEGRA124_CLK_BSEV 63 /* 64 */ #define TEGRA124_CLK_UARTD 65 /* 66 */ #define TEGRA124_CLK_I2C3 67 #define TEGRA124_CLK_SBC4 68 #define TEGRA124_CLK_SDMMC3 69 #define TEGRA124_CLK_PCIE 70 #define TEGRA124_CLK_OWR 71 #define TEGRA124_CLK_AFI 72 #define TEGRA124_CLK_CSITE 73 /* 74 */ /* 75 */ #define TEGRA124_CLK_LA 76 #define TEGRA124_CLK_TRACE 77 #define TEGRA124_CLK_SOC_THERM 78 #define TEGRA124_CLK_DTV 79 /* 80 */ #define TEGRA124_CLK_I2CSLOW 81 #define TEGRA124_CLK_DSIB 82 #define TEGRA124_CLK_TSEC 83 /* 84 */ /* 85 */ /* 86 */ /* 87 */ /* 88 */ #define TEGRA124_CLK_XUSB_HOST 89 /* 90 */ #define TEGRA124_CLK_MSENC 91 #define TEGRA124_CLK_CSUS 92 /* 93 */ /* 94 */ /* 95 (bit affects xusb_dev and xusb_dev_src) */ /* 96 */ /* 97 */ /* 98 */ #define TEGRA124_CLK_MSELECT 99 #define TEGRA124_CLK_TSENSOR 100 #define TEGRA124_CLK_I2S3 101 #define TEGRA124_CLK_I2S4 102 #define TEGRA124_CLK_I2C4 103 #define TEGRA124_CLK_SBC5 104 #define TEGRA124_CLK_SBC6 105 #define TEGRA124_CLK_D_AUDIO 106 #define TEGRA124_CLK_APBIF 107 #define TEGRA124_CLK_DAM0 108 #define TEGRA124_CLK_DAM1 109 #define TEGRA124_CLK_DAM2 110 #define TEGRA124_CLK_HDA2CODEC_2X 111 /* 112 */ #define TEGRA124_CLK_AUDIO0_2X 113 #define TEGRA124_CLK_AUDIO1_2X 114 #define TEGRA124_CLK_AUDIO2_2X 115 #define TEGRA124_CLK_AUDIO3_2X 116 #define TEGRA124_CLK_AUDIO4_2X 117 #define TEGRA124_CLK_SPDIF_2X 118 #define TEGRA124_CLK_ACTMON 119 #define TEGRA124_CLK_EXTERN1 120 #define TEGRA124_CLK_EXTERN2 121 #define TEGRA124_CLK_EXTERN3 122 #define TEGRA124_CLK_SATA_OOB 123 #define TEGRA124_CLK_SATA 124 #define TEGRA124_CLK_HDA 125 /* 126 */ #define TEGRA124_CLK_SE 127 #define TEGRA124_CLK_HDA2HDMI 128 #defin