MAJOR=4
MINOR=11
DEVNAME=tty11
  *   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿ¿685_†I|¥+ÂÄ ­    /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/*
 * Copyright (c) 2005-2006 Intel Corporation.  All rights reserved.
 */

#ifndef IB_USER_MARSHALL_H
#define IB_USER_MARSHALL_H

#include <rdma/ib_verbs.h>
#include <rdma/ib_sa.h>
#include <rdma/ib_user_verbs.h>
#include <rdma/ib_user_sa.h>

void ib_copy_qp_attr_to_user(struct ib_device *device,
			     struct ib_uverbs_qp_attr *dst,
			     struct ib_qp_attr *src);

void ib_copy_ah_attr_to_user(struct ib_device *device,
			     struct ib_uverbs_ah_attr *dst,
			     struct rdma_ah_attr *src);

void ib_copy_path_rec_to_user(struct ib_user_path_rec *dst,
			      struct sa_path_rec *src);

#endif /* IB_USER_MARSHALL_H */
  #   ˆ¿ÀƒyÖß¾a–Ðz¾””ÔD¨ 	ÅŒ½p©‹FÿÅ "7    /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2018-2019 NXP
 */

#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
#define __DT_BINDINGS_CLOCK_IMX8MN_H

#define IMX8MN_CLK_DUMMY			0
#define IMX8MN_CLK_32K				1
#define IMX8MN_CLK_24M				2
#define IMX8MN_OSC_HDMI_CLK			3
#define IMX8MN_CLK_EXT1				4
#define IMX8MN_CLK_EXT2				5
#define IMX8MN_CLK_EXT3				6
#define IMX8MN_CLK_EXT4				7
#define IMX8MN_AUDIO_PLL1_REF_SEL		8
#define IMX8MN_AUDIO_PLL2_REF_SEL		9
#define IMX8MN_VIDEO_PLL_REF_SEL		10
#define IMX8MN_VIDEO_PLL1_REF_SEL		IMX8MN_VIDEO_PLL_REF_SEL
#define IMX8MN_DRAM_PLL_REF_SEL			11
#define IMX8MN_GPU_PLL_REF_SEL			12
#define IMX8MN_M7_ALT_PLL_REF_SEL		13
#define IMX8MN_VPU_PLL_REF_SEL			IMX8MN_M7_ALT_PLL_REF_SEL
#define IMX8MN_ARM_PLL_REF_SEL			14
#define IMX8MN_SYS_PLL1_REF_SEL			15
#define IMX8MN_SYS_PLL2_REF_SEL			16
#define IMX8MN_SYS_PLL3_REF_SEL			17
#define IMX8MN_AUDIO_PLL1			18
#define IMX8MN_AUDIO_PLL2			19
#define IMX8MN_VIDEO_PLL			20
#define IMX8MN_VIDEO_PLL1			IMX8MN_VIDEO_PLL
#define IMX8MN_DRAM_PLL				21
#define IMX8MN_GPU_PLL				22
#define IMX8MN_M7_ALT_PLL			23
#define IMX8MN_VPU_PLL				IMX8MN_M7_ALT_PLL
#define IMX8MN_ARM_PLL				24
#define IMX8MN_SYS_PLL1				25
#define IMX8MN_SYS_PLL2				26
#define IMX8MN_SYS_PLL3				27
#define IMX8MN_AUDIO_PLL1_BYPASS		28
#define IMX8MN_AUDIO_PLL2_BYPASS		29
#define IMX8MN_VIDEO_PLL_BYPASS			30
#define IMX8MN_VIDEO_PLL1_BYPASS		IMX8MN_VIDEO_PLL_BYPASS
#define IMX8MN_DRAM_PLL_BYPASS			31
#define IMX8MN_GPU_PLL_BYPASS			32
#define IMX8MN_M7_ALT_PLL_BYPASS		33
#define IMX8MN_VPU_PLL_BYPASS			IMX8MN_M7_ALT_PLL_BYPASS
#define IMX8MN_ARM_PLL_BYPASS			34
#define IMX8MN_SYS_PLL1_BYPASS			35
#define IMX8MN_SYS_PLL2_BYPASS			36
#define IMX8MN_SYS_PLL3_BYPASS			37
#define IMX8MN_AUDIO_PLL1_OUT			38
#define IMX8MN_AUDIO_PLL2_OUT			39
#define IMX8MN_VIDEO_PLL_OUT			40
#define IMX8MN_VIDEO_PLL1_OUT			IMX8MN_VIDEO_PLL_OUT
#define IMX8MN_DRAM_PLL_OUT			41
#define IMX8MN_GPU_PLL_OUT			42
#define IMX8MN_M7_ALT_PLL_OUT			43
#define IMX8MN_VPU_PLL_OUT			IMX8MN_M7_ALT_PLL_OUT
#define IMX8MN_ARM_PLL_OUT			44
#define IMX8MN_SYS_PLL1_OUT			45
#define IMX8MN_SYS_PLL2_OUT			46
#define IMX8MN_SYS_PLL3_OUT			47
#define IMX8MN_SYS_PLL1_40M			48
#define IMX8MN_SYS_PLL1_80M			49
#define IMX8MN_SYS_PLL1_100M			50
#define IMX8MN_SYS_PLL1_133M			51
#define IMX8MN_SYS_PLL1_160M			52
#define IMX8MN_SYS_PLL1_200M			53
#define IMX8MN_SYS_PLL1_266M			54
#define IMX8MN_SYS_PLL1_400M			55
#define IMX8MN_SYS_PLL1_800M			56
#define IMX8MN_SYS_PLL2_50M			57
#define IMX8MN_SYS_PLL2_100M			58
#define IMX8MN_SYS_PLL2_125M			59
#define IMX8MN_SYS_PLL2_166M			60
#define IMX8MN_SYS_PLL2_200M			61
#define IMX8MN_SYS_PLL2_250M			62
#define IMX8MN_SYS_PLL2_333M			63
#define IMX8MN_SYS_PLL2_500M			64
#define IMX8MN_SYS_PLL2_1000M			65

/* CORE CLOCK ROOT */
#define IMX8MN_CLK_A53_SRC			66
#define IMX8MN_CLK_GPU_CORE_SRC			67
#define IMX8MN_CLK_GPU_SHADER_SRC		68
#define IMX8MN_CLK_A53_CG			69
#define IMX8MN_CLK_GPU_CORE_CG			70
#define IMX8MN_CLK_GPU_SHADER_CG		71
#define IMX8MN_CLK_A53_DIV			72
#define IMX8MN_CLK_GPU_CORE_DIV			73
#define IMX8MN_CLK_GPU_SHADER_DIV		74

/* BUS CLOCK ROOT */
#define IMX8MN_CLK_MAIN_AXI			75
#define IMX8MN_CLK_ENET_AXI			76
#define IMX8MN_CLK_NAND_USDHC_BUS		77
#define IMX8MN