0 *l4( (  fB- y_I|+!-/* SPDX-License-Identifier: GPL-2.0-only */ /* * Functions to access LP873X power management chip. * * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __LINUX_MFD_LP873X_H #define __LINUX_MFD_LP873X_H #include #include #include /* LP873x chip id list */ #define LP873X 0x00 /* All register addresses */ #define LP873X_REG_DEV_REV 0X00 #define LP873X_REG_OTP_REV 0X01 #define LP873X_REG_BUCK0_CTRL_1 0X02 #define LP873X_REG_BUCK0_CTRL_2 0X03 #define LP873X_REG_BUCK1_CTRL_1 0X04 #define LP873X_REG_BUCK1_CTRL_2 0X05 #define LP873X_REG_BUCK0_VOUT 0X06 #define LP873X_REG_BUCK1_VOUT 0X07 #define LP873X_REG_LDO0_CTRL 0X08 #define LP873X_REG_LDO1_CTRL 0X09 #define LP873X_REG_LDO0_VOUT 0X0A #define LP873X_REG_LDO1_VOUT 0X0B #define LP873X_REG_BUCK0_DELAY 0X0C #define LP873X_REG_BUCK1_DELAY 0X0D #define LP873X_REG_LDO0_DELAY 0X0E #define LP873X_REG_LDO1_DELAY 0X0F #define LP873X_REG_GPO_DELAY 0X10 #define LP873X_REG_GPO2_DELAY 0X11 #define LP873X_REG_GPO_CTRL 0X12 #define LP873X_REG_CONFIG 0X13 #define LP873X_REG_PLL_CTRL 0X14 #define LP873X_REG_PGOOD_CTRL1 0X15 #define LP873X_REG_PGOOD_CTRL2 0X16 #define LP873X_REG_PG_FAULT 0X17 #define LP873X_REG_RESET 0X18 #define LP873X_REG_INT_TOP_1 0X19 #define LP873X_REG_INT_TOP_2 0X1A #define LP873X_REG_INT_BUCK 0X1B #define LP873X_REG_INT_LDO 0X1C #define LP873X_REG_TOP_STAT 0X1D #define LP873X_REG_BUCK_STAT 0X1E #define LP873X_REG_LDO_STAT 0x1F #define LP873X_REG_TOP_MASK_1 0x20 #define LP873X_REG_TOP_MASK_2 0x21 #define LP873X_REG_BUCK_MASK 0x22 #define LP873X_REG_LDO_MASK 0x23 #define LP873X_REG_SEL_I_LOAD 0x24 #define LP873X_REG_I_LOAD_2 0x25 #define LP873X_REG_I_LOAD_1 0x26 #define LP873X_REG_MAX LP873X_REG_I_LOAD_1 /* Register field definitions */ #define LP873X_DEV_REV_DEV_ID 0xC0 #define LP873X_DEV_REV_ALL_LAYER 0x30 #define LP873X_DEV_REV_METAL_LAYER 0x0F #define LP873X_OTP_REV_OTP_ID 0xFF #define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3) #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2) #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1) #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0) #define LP873X_BUCK0_CTRL_2_BUCK0_ILIM 0x38 #define LP873X_BUCK0_CTRL_2_BUCK0_SLEW_RATE 0x07 #define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3) #define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2) #define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1) #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0) #define LP873X_BUCK1_CTRL_2_BUCK1_ILIM 0x38 #define LP873X_BUCK1_CTRL_2_BUCK1_SLEW_RATE 0x07 #define LP873X_BUCK0_VOUT_BUCK0_VSET 0xFF #define LP873X_BUCK1_VOUT_BUCK1_VSET 0xFF #define LP873X_LDO0_CTRL_LDO0_RDIS_EN BIT(2) #define LP873X_LDO0_CTRL_LDO0_EN_PIN_CTRL BIT(1) #define LP873X_LDO0_CTRL_LDO0_EN BIT(0) #define LP873X_LDO1_CTRL_LDO1_RDIS_EN BIT(2) #define LP873X_LDO1_CTRL_LDO1_EN_PIN_CTRL BIT(1) #define LP873X_LDO1_CTRL_LDO1_EN BIT(0) #define LP873X_LDO0_VOUT_LDO0_VSET 0x1F #define LP873X_LDO1_VOUT_LDO1_VSET 0x1F #define LP873X_BUCK0_DELAY_BUCK0_SD_DELAY 0xF0 #define LP873X_BUCK0_DELAY_BUCK0_SU_DELAY 0x0F #define LP873X_BUCK1_DELAY_BUCK1_SD_DELAY 0xF0 #define LP873X_BUCK1_DELAY_BUCK1_SU_DELAY 0x0F #define LP873X_LDO0_DELAY_LDO0_SD_DELAY 0xF0 #define LP873X_LDO0_DELAY_LDO0_SU_DELAY 0x0F #define LP873X_LDO1_DELAY_LDO1_SD_DELAY 0xF0 #define LP873X_LDO1_DELAY_LDO1_SU_DELAY 0x0F #define LP873X_GPO_DELAY_GPO_SD_DELAY 0xF0 #define LP873X_GPO_DELAY_GPO_SU_DELAY 0x0F #define LP873X_GPO2_DELAY_GPO2_SD_DELAY 0xF0 #define LP873X_GPO2_DELAY_GPO2_SU_DELAY 0x0F #define LP873X_GPO_CTRL_GPO2_OD BIT(6) #define LP873X_GPO_CTRL_GPO2_EN_PIN_CTRL BIT(5) #define LP873X_GPO_CTRL_GPO2_EN BIT(4) #define LP873X_GPO_CTRL_GPO_OD BIT(2) #define LP873X_GPO_CTRL_GPO_EN_PIN_CTRL BIT(1) #define LP873X_GPO_CTRL_GPO_EN BIT(0) #define LP873X_CONFIG_SU_DELAY_SEL BIT(6) #define LP873X_CONFIG_SD_DELAY_SEL BIT(5) #define LP873X_CONFIG_CLKIN_PIN_SEL BIT(4) #define LP873X_CONFIG_CLKIN_PD BIT