0   m Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/class/tty/tty9/subsystem/tty8

Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/class/tty/tty9/subsystem/tty8

 NameLast modifiedSizeDescription
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 dev 2026-10-12 22:02 4.0K 
 power/ 2026-10-12 22:02 -  
 subsystem/ 2026-10-11 21:02 -  
 uevent 2026-10-12 22:02 4.0K 
. _I|Mjq؂ai~ *j"T BS File not found.   File not found. *l4( (  fB- iE_I|+l/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ #define _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ struct regmap; struct clk; struct mx25_tsadc { struct regmap *regs; struct irq_domain *domain; struct clk *clk; }; #define MX25_TSC_TGCR 0x00 #define MX25_TSC_TGSR 0x04 #define MX25_TSC_TICR 0x08 /* The same register layout for TC and GC queue */ #define MX25_ADCQ_FIFO 0x00 #define MX25_ADCQ_CR 0x04 #define MX25_ADCQ_SR 0x08 #define MX25_ADCQ_MR 0x0c #define MX25_ADCQ_ITEM_7_0 0x20 #define MX25_ADCQ_ITEM_15_8 0x24 #define MX25_ADCQ_CFG(n) (0x40 + ((n) * 0x4)) #define MX25_ADCQ_MR_MASK 0xffffffff /* TGCR */ #define MX25_TGCR_PDBTIME(x) ((x) << 25) #define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25) #define MX25_TGCR_PDBEN BIT(24) #define MX25_TGCR_PDEN BIT(23) #define MX25_TGCR_ADCCLKCFG(x) ((x) << 16) #define MX25_TGCR_GET_ADCCLK(x) (((x) >> 16) & 0x1f) #define MX25_TGCR_INTREFEN BIT(10) #define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8) #define MX25_TGCR_POWERMODE_SAVE (1 << 8) #define MX25_TGCR_POWERMODE_ON (2 << 8) #define MX25_TGCR_STLC BIT(5) #define MX25_TGCR_SLPC BIT(4) #define MX25_TGCR_FUNC_RST BIT(2) #define MX25_TGCR_TSC_RST BIT(1) #define MX25_TGCR_CLK_EN BIT(0) /* TGSR */ #define MX25_TGSR_SLP_INT BIT(2) #define MX25_TGSR_GCQ_INT BIT(1) #define MX25_TGSR_TCQ_INT BIT(0) /* ADCQ_ITEM_* */ #define _MX25_ADCQ_ITEM(item, x) ((x) << ((item) * 4)) #define MX25_ADCQ_ITEM(item, x) ((item) >= 8 ? \ _MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x))) /* ADCQ_FIFO (TCQFIFO and GCQFIFO) */ #define MX25_ADCQ_FIFO_DATA(x) (((x) >> 4) & 0xfff) #define MX25_ADCQ_FIFO_ID(x) ((x) & 0xf) /* ADCQ_CR (TCQR and GCQR) */ #define MX25_ADCQ_CR_PDCFG_LEVEL BIT(19) #define MX25_ADCQ_CR_PDMSK BIT(18) #define MX25_ADCQ_CR_FRST BIT(17) #define MX25_ADCQ_CR_QRST BIT(16) #define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12) #define MX25_ADCQ_CR_RWAIT(x) ((x) << 12) #define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8) #define MX25_ADCQ_CR_WMRK(x) ((x) << 8) #define MX25_ADCQ_CR_LITEMID_MASK (0xf << 4) #define MX25_ADCQ_CR_LITEMID(x) ((x) << 4) #define MX25_ADCQ_CR_RPT BIT(3) #define MX25_ADCQ_CR_FQS BIT(2) #define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0) #define MX25_ADCQ_CR_QSM_PD 0x1 #define MX25_ADCQ_CR_QSM_FQS 0x2 #define MX25_ADCQ_CR