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Index of /FSS-OZR/root/proc/self/cwd/sys/class/ata_link/link1
Index of /FSS-OZR/root/proc/self/cwd/sys/class/ata_link/link1
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k_I|+ /* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
#ifndef __ABI_MACH_T194_POWERGATE_T194_H_
#define __ABI_MACH_T194_POWERGATE_T194_H_
#define TEGRA194_POWER_DOMAIN_AUD 1
#define TEGRA194_POWER_DOMAIN_DISP 2
#define TEGRA194_POWER_DOMAIN_DISPB 3
#define TEGRA194_POWER_DOMAIN_DISPC 4
#define TEGRA194_POWER_DOMAIN_ISPA 5
#define TEGRA194_POWER_DOMAIN_NVDECA 6
#define TEGRA194_POWER_DOMAIN_NVJPG 7
#define TEGRA194_POWER_DOMAIN_NVENCA 8
#define TEGRA194_POWER_DOMAIN_NVENCB 9
#define TEGRA194_POWER_DOMAIN_NVDECB 10
#define TEGRA194_POWER_DOMAIN_SAX 11
#define TEGRA194_POWER_DOMAIN_VE 12
#define TEGRA194_POWER_DOMAIN_VIC 13
#define TEGRA194_POWER_DOMAIN_XUSBA 14
#define TEGRA194_POWER_DOMAIN_XUSBB 15
#define TEGRA194_POWER_DOMAIN_XUSBC 16
#define TEGRA194_POWER_DOMAIN_PCIEX8A 17
#define TEGRA194_POWER_DOMAIN_PCIEX4A 18
#define TEGRA194_POWER_DOMAIN_PCIEX1A 19
#define TEGRA194_POWER_DOMAIN_PCIEX8B 21
#define TEGRA194_POWER_DOMAIN_PVAA 22
#define TEGRA194_POWER_DOMAIN_PVAB 23
#define TEGRA194_POWER_DOMAIN_DLAA 24
#define TEGRA194_POWER_DOMAIN_DLAB 25
#define TEGRA194_POWER_DOMAIN_CV 26
#define TEGRA194_POWER_DOMAIN_GPU 27
#define TEGRA194_POWER_DOMAIN_MAX 27
#endif
0 !
!/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for the Qualcomm PMIC's
* Multi-Purpose Pin binding.
*/
#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
/* power-source */
/* Digital Input/Output: level [PM8058] */
#define PM8058_MPP_VPH 0
#define PM8058_MPP_S3 1
#define PM8058_MPP_L2 2
#define PM8058_MPP_L3 3
/* Digital Input/Output: level [PM8901] */
#define PM8901_MPP_MSMIO 0
#define PM8901_MPP_DIG 1
#define PM8901_MPP_L5 2
#define PM8901_MPP_S4 3
#define PM8901_MPP_VPH 4
/* Digital Input/Output: level [PM8921] */
#define PM8921_MPP_S4 1
#define PM8921_MPP_L15