live @ l4( (  fB- "_I|+am_J*j"Tz]ţ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _CRYPTO_CAST_COMMON_H #define _CRYPTO_CAST_COMMON_H extern const u32 cast_s1[256]; extern const u32 cast_s2[256]; extern const u32 cast_s3[256]; extern const u32 cast_s4[256]; #endif " lm_J 4 jbѿ  Cryptsetup 1.6.1 Release Notes ============================== Changes since version 1.6.0 * Fix loop-AES keyfile parsing. Loop-AES keyfile should be text keyfile, reject keyfiles which are not properly terminated. * Fix passphrase pool overflow for too long TCRYPT passphrase. (Maximal TCRYPT passphrase length is 64 characters.) * Return EPERM (translated to exit code 2) for too long TCRYPT passphrase. * Fix deactivation of device when failed underlying node disappeared. * Fix API deactivate call for TCRYPT format and NULL context parameter. * Improve keyslot checker example documentation. * Report error message if deactivation fails and device is still busy. * Make passphrase prompts more consistent (and remove "LUKS" form prompt). * Fix some missing headers (compilation failed with alternative libc). * Remove not functional API UUID support for plain & loopaes devices. (not persistent activation UUID). * Properly cleanup devices on interrupt in api-test. * Support all tests run if kernel is in FIPS mode.   935_I|Mdv &K Index of /anon_sym/anon/proc/thread-self/root/lib64/llvm

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  t/* SPDX-License-Identifier: GPL-2.0 */ /* * Prevent the compiler from merging or refetching reads or writes. The * compiler is also forbidden from reordering successive instances of * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some * particular ordering. One way to make the compiler aware of ordering is to * put the two invocations of READ_ONCE or WRITE_ONCE in different C * statements. * * These two macros will also work on aggregate data types like structs or * unions. * * Their two major use cases are: (1) Mediating communication between * process-level code and irq/NMI handlers, all running on the same CPU, * and (2) Ensuring that the compiler does not fold, spindle, or otherwise * mutilate accesses that either do not require ordering or that interact * with an explicit memory barrier or atomic instruction that provides the * required ordering. */ #ifndef __ASM_GENERIC_RWONCE_H #define __ASM_GENERIC_RWONCE_H #ifndef __ASSEMBLY__ #include #include #include /* * Yes, this permits 64-bit accesses on 32-bit architectures. These will * actually be atomic in some cases (namely Armv7 + LPAE), but for others we * rely on the access being split into 2x32-bit accesses for a 32-bit quantity * (e.g. a virtual address) and a strong prevailing wind. */ #define compiletime_assert_rwonce_type(t) \ compiletime_assert(__native_word(t) || sizeof(t) == sizeof(long long), \ "Unsupported access size for {READ,WRITE}_ONCE().") /* * Use __READ_ONCE() instead of READ_ONCE() if you do not require any * atomicity. Note that this may resul