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Index of /anon_sym/anon/usr/share/doc/cpanel-php84-xml-rpc
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e þ 1/* SPDX-License-Identifier: GPL-2.0 */
#ifndef MFD_TMIO_H
#define MFD_TMIO_H
#include
#include
#include
#include
#include
#include
#include
#define tmio_ioread8(addr) readb(addr)
#define tmio_ioread16(addr) readw(addr)
#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
#define tmio_ioread32(addr) \
(((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
#define tmio_iowrite8(val, addr) writeb((val), (addr))
#define tmio_iowrite16(val, addr) writew((val), (addr))
#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
#define tmio_iowrite32(val, addr) \
do { \
writew((val), (addr)); \
writew((val) >> 16, (addr) + 2); \
} while (0)
#define sd_config_write8(base, shift, reg, val) \
tmio_iowrite8((val), (base) + ((reg) << (shift)))
#define sd_config_write16(base, shift, reg, val) \
tmio_iowrite16((val), (base) + ((reg) << (shift)))
#define sd_config_write32(base, shift, reg, val) \
do { \
tmio_iowrite16((val), (base) + ((reg) << (shift))); \
tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
} while (0)
/* tmio MMC platform flags */
/*
* Some controllers can support a 2-byte block size when the bus width
* is configured in 4-bit mode.
*/
#define TMIO_MMC_BLKSZ_2BYTES BIT(1)
/*
* Some controllers can support SDIO IRQ signalling.
*/
#define TMIO_MMC_SDIO_IRQ BIT(2)
/* Some features are only available or tested on R-Car Gen2 or later */
#define TMIO_MMC_MIN_RCAR2 BIT(3)
/*
* Some controllers require waiting for the SD bus to become
* idle before writing to some registers.
*/
#define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
/*
* Use the busy timeout feature. Probably all TMIO versions support it. Yet,
* we don't have documentation for old variants, so we enable only known good
* variants with this flag. Can be removed once all variants are known good.
*/
#define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5)
/*
* Some controllers have CMD12 automatically
* issue/non-issue register
*/
#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7)
/* Controller has some SDIO status bits which must be 1 */
#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8)
/*
* Some controllers have a 32-bit wide data port register
*/
#define TMIO_MMC_32BIT_DATA_PORT BIT(9)
/*
* Some controllers allows to set SDx actual clock
*/
#define TMIO_MMC_CLK_ACTUAL BIT(10)
/* Some controllers have a CBSY bit */
#define TMIO_MMC_HAVE_CBSY BIT(11)
int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
struct dma_chan;
/*
* data for the MMC controller
*/
struct tmio_mmc_data {
void *chan_priv_tx;
void *chan_priv_rx;
unsigned int hclk;
unsigned long capabilities;
unsigned long capabilities2;
unsigned long flags;
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