DEVTYPE=port DRIVER=port +l4( (  fD- h_I|+?/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_CPUFEATURES_H #define _ASM_X86_CPUFEATURES_H #ifndef _ASM_X86_REQUIRED_FEATURES_H #include #endif #ifndef _ASM_X86_DISABLED_FEATURES_H #include #endif /* * Defines x86 CPU feature bits * * These have been expanded for RH_KABI. */ #define NCAPINTS 30 /* N 32-bit words worth of info */ #define NBUGINTS 2 /* N 32-bit bug flags */ /* * Note: If the comment begins with a quoted string, that string is used * in /proc/cpuinfo instead of the macro name. Otherwise, this feature * bit is not displayed in /proc/cpuinfo at all. * * When adding new features here that depend on other features, * please update the table in kernel/cpu/cpuid-deps.c as well. */ /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ #define X86_FEATURE_FPU ( 0*32+ 0) /* "fpu" Onboard FPU */ #define X86_FEATURE_VME ( 0*32+ 1) /* "vme" Virtual Mode Extensions */ #define X86_FEATURE_DE ( 0*32+ 2) /* "de" Debugging Extensions */ #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */ #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */ #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */ #define X86_FEATURE_PAE ( 0*32+ 6) /* "pae" Physical Address Extensions */ #define X86_FEATURE_MCE ( 0*32+ 7) /* "mce" Machine Check Exception */ #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */ #define X86_FEATURE_APIC ( 0*32+ 9) /* "apic" Onboard APIC */ #define X86_FEATURE_SEP ( 0*32+11) /* "sep" SYSENTER/SYSEXIT */ #define X86_FEATURE_MTRR ( 0*32+12) /* "mtrr" Memory Type Range Registers */ #define X86_FEATURE_PGE ( 0*32+13) /* "pge" Page Global Enable */ #define X86_FEATURE_MCA ( 0*32+14) /* "mca" Machine Check Architecture */ #define X86_FEATURE_CMOV ( 0*32+15) /* "cmov" CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ #define X86_FEATURE_PAT ( 0*32+16) /* "pat" Page Attribute Table */ #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */ #define X86_FEATURE_PN ( 0*32+18) /* "pn" Processor serial number */ #define X86_FEATURE_CLFLUSH ( 0*32+19) /* "clflush" CLFLUSH instruction */ #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ #define X86_FEATURE_ACPI ( 0*32+22) /* "acpi" ACPI via MSR */ #define X86_FEATURE_MMX ( 0*32+23) /* "mmx" Multimedia Extensions */ #define X86_FEATURE_FXSR ( 0*32+24) /* "fxsr" FXSAVE/FXRSTOR, CR4.OSFXSR */ #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */ #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */ #define X86_FEATURE_PBE ( 0*32+31) /* "pbe" Pending Break Enable */ /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ /* Don't duplicate feature flags which are redundant with Intel! */ #define X86_FEATURE_SYSCALL ( 1*32+11) /* "syscall" SYSCALL/SYSRET */ #define X86_FEATURE_MP ( 1*32+19) /* "mp" MP Capable */ #define X86_FEATURE_NX ( 1*32+20) /* "nx" Execute Disable */ #define X86_FEATURE_MMXEXT ( 1*32+22) /* "mmxext" AMD MMX extensions */ #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* "fxsr_opt" FXSAVE/FXRSTOR optimizations */ #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ #define X86_FEATURE_RDTSCP ( 1*32+27) /* "rdtscp" RDTSCP */ #define X86_FEATURE_LM ( 1*32+29) /* "lm" Long Mode (x86-64, 64-bit support) */ #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* "3dnowext" AMD 3DNow extensions */ #define X86_FEATURE_3DNOW ( 1*32+31) /* "3dnow" 3DNow */ /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* "recovery" CPU in recovery mode */ #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* "longrun" Longrun power control */ #define X86_FEATURE_LR