16 *3l4( (  fB- y_I|+"03/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _DT_BINDINGS_CLK_MT6765_H #define _DT_BINDINGS_CLK_MT6765_H /* FIX Clks */ #define CLK_TOP_CLK26M 0 /* APMIXEDSYS */ #define CLK_APMIXED_ARMPLL_L 0 #define CLK_APMIXED_ARMPLL 1 #define CLK_APMIXED_CCIPLL 2 #define CLK_APMIXED_MAINPLL 3 #define CLK_APMIXED_MFGPLL 4 #define CLK_APMIXED_MMPLL 5 #define CLK_APMIXED_UNIV2PLL 6 #define CLK_APMIXED_MSDCPLL 7 #define CLK_APMIXED_APLL1 8 #define CLK_APMIXED_MPLL 9 #define CLK_APMIXED_ULPOSC1 10 #define CLK_APMIXED_ULPOSC2 11 #define CLK_APMIXED_SSUSB26M 12 #define CLK_APMIXED_APPLL26M 13 #define CLK_APMIXED_MIPIC0_26M 14 #define CLK_APMIXED_MDPLLGP26M 15 #define CLK_APMIXED_MMSYS_F26M 16 #define CLK_APMIXED_UFS26M 17 #define CLK_APMIXED_MIPIC1_26M 18 #define CLK_APMIXED_MEMPLL26M 19 #define CLK_APMIXED_CLKSQ_LVPLL_26M 20 #define CLK_APMIXED_MIPID0_26M 21 #define CLK_APMIXED_NR_CLK 22 /* TOPCKGEN */ #define CLK_TOP_SYSPLL 0 #define CLK_TOP_SYSPLL_D2 1 #define CLK_TOP_SYSPLL1_D2 2 #define CLK_TOP_SYSPLL1_D4 3 #define CLK_TOP_SYSPLL1_D8 4 #define CLK_TOP_SYSPLL1_D16 5 #define CLK_TOP_SYSPLL_D3 6 #define CLK_TOP_SYSPLL2_D2 7 #define CLK_TOP_SYSPLL2_D4 8 #define CLK_TOP_SYSPLL2_D8 9 #define CLK_TOP_SYSPLL_D5 10 #define CLK_TOP_SYSPLL3_D2 11 #define CLK_TOP_SYSPLL3_D4 12 #define CLK_TOP_SYSPLL_D7 13 #define CLK_TOP_SYSPLL4_D2 14 #define CLK_TOP_SYSPLL4_D4 15 #define CLK_TOP_USB20_192M 16 #define CLK_TOP_USB20_192M_D4 17 #define CLK_TOP_USB20_192M_D8 18 #define CLK_TOP_USB20_192M_D16 19 #define CLK_TOP_USB20_192M_D32 20 #define CLK_TOP_UNIVPLL 21 #define CLK_TOP_UNIVPLL_D2 22 #define CLK_TOP_UNIVPLL1_D2 23 #define CLK_TOP_UNIVPLL1_D4 24 #define CLK_TOP_UNIVPLL_D3 25 #define CLK_TOP_UNIVPLL2_D2 26 #define CLK_TOP_UNIVPLL2_D4 27 #define CLK_TOP_UNIVPLL2_D8 28 #define CLK_TOP_UNIVPLL2_D32 29 #define CLK_TOP_UNIVPLL_D5 30 #define CLK_TOP_UNIVPLL3_D2 31 #define CLK_TOP_UNIVPLL3_D4 32 #define CLK_TOP_MMPLL 33 #define CLK_TOP_MMPLL_D2 34 #define CLK_TOP_MPLL 35 #define CLK_TOP_DA_MPLL_104M_DIV 36 #define CLK_TOP_DA_MPLL_52M_DIV 37 #define CLK_TOP_MFGPLL 38 #define CLK_TOP_MSDCPLL 39 #define CLK_TOP_MSDCPLL_D2 40 #define CLK_TOP_APLL1 41 #define CLK_TOP_APLL1_D2 42 #define CLK_TOP_APLL1_D4 43 #define CLK_TOP_APLL1_D8 44 #define CLK_TOP_ULPOSC1 45 #define CLK_TOP_ULPOSC1_D2 46 #define CLK_TOP_ULPOSC1_D4 47 #define CLK_TOP_ULPOSC1_D8 48 #define CLK_TOP_ULPOSC1_D16 49 #define CLK_TOP_ULPOSC1_D32 50 #define CLK_TOP_DMPLL 51 #define CLK_TOP_F_FRTC 52 #define CLK_TOP_F_F26M 53 #define CLK_TOP_AXI 54 #define CLK_TOP_MM 55 #define CLK_TOP_SCP 56 #define CLK_TOP_MFG 57 #define CLK_TOP_F_FUART 58 #define CLK_TOP_SPI 59 #define CLK_TOP_MSDC50_0 60 #define CLK_TOP_MSDC30_1 61 #define CLK_TOP_AUDIO 62 #define CLK_TOP_AUD_1 63 #define CLK_TOP_AUD_ENGEN1 64 #define CLK_TOP_F_FDISP_PWM 65 #define CLK_TOP_SSPM 66 #define CLK_TOP_DXCC 67 #define CLK_TOP_I2C 68 #define CLK_TOP_F_FPWM 69 #define CLK_TOP_F_FSENINF 70 #define CLK_TOP_AES_FDE 71 #define CLK_TOP_F_BIST2FPC 72 #define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 #define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 #define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 #define CLK_TOP_DA_USB20_48M_DIV 76 #define CLK_TOP_DA_UNIV_48M_DIV 77 #define CLK_TOP_APLL12_DIV0 78 #define CLK_TOP_APLL12_DIV1 79 #define CLK_TOP_APLL12_DIV2 80 #define CLK_TOP_APLL12_DIV3 81 #define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 #define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 #define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 #define CLK_TOP_FMEM_OCC_DRC_EN 85 #define CLK_TOP_USB20_48M_EN 86 #define CLK_TOP_UNIVPLL_48M_EN 87 #define CLK_TOP_MPLL_104M_EN 88 #define CLK_TOP_MPLL_52M_EN 89 #define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 #define CLK_TOP_F_BIST2FPC_EN 91 #define CLK_TOP_MD_32K 92 #define CLK_TOP_MD_26M 93 #define CLK_TOP_MD2_32K 94 #define CLK_TOP_MD2_26M 95 #define CLK_TOP_AXI_SEL 96 #define CLK_TOP_MEM_SEL 97 #define CLK_TOP_MM_SEL 98 #define CLK_TOP_SCP_SEL 99 #define CLK_TOP_