PNP0C0F
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 *
 * (c) 2004 Simtec Electronics
 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
 *
 * Header file for Epson S1D13XXX driver code
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file COPYING in the main directory of this archive for
 * more details.
 */

#ifndef	S1D13XXXFB_H
#define	S1D13XXXFB_H

#define S1D_PALETTE_SIZE		256
#define S1D_FBID			"S1D13xxx"
#define S1D_DEVICENAME			"s1d13xxxfb"

/* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
#define S1D13505_PROD_ID		0x3	/* 000011 */
#define S1D13506_PROD_ID		0x4	/* 000100 */
#define S1D13806_PROD_ID		0x7	/* 000111 */

/* register definitions (tested on s1d13896) */
#define S1DREG_REV_CODE			0x0000	/* Prod + Rev Code Register */
#define S1DREG_MISC			0x0001	/* Miscellaneous Register */
#define S1DREG_GPIO_CNF0		0x0004	/* General IO Pins Configuration Register 0 */
#define S1DREG_GPIO_CNF1		0x0005	/* General IO Pins Configuration Register 1 */
#define S1DREG_GPIO_CTL0		0x0008	/* General IO Pins Control Register 0 */
#define S1DREG_GPIO_CTL1		0x0009	/* General IO Pins Control Register 1 */
#define S1DREG_CNF_STATUS		0x000C	/* Configuration Status Readback Register */
#define S1DREG_CLK_CNF			0x0010	/* Memory Clock Configuration Register */
#define S1DREG_LCD_CLK_CNF		0x0014	/* LCD Pixel Clock Configuration Register */
#define S1DREG_CRT_CLK_CNF		0x0018	/* CRT/TV Pixel Clock Configuration Register */
#define S1DREG_MPLUG_CLK_CNF		0x001C	/* MediaPlug Clock Configuration Register */
#define S1DREG_CPU2MEM_WST_SEL		0x001E	/* CPU To Memory Wait State Select Register */
#define S1DREG_MEM_CNF			0x0020	/* Memory Configuration Register */
#define S1DREG_SDRAM_REF_RATE		0x0021	/* SDRAM Refresh Rate Register */
#define S1DREG_SDRAM_TC0		0x002A	/* SDRAM Timing Control Register 0 */
#define S1DREG_SDRAM_TC1		0x002B	/* SDRAM Timing Control Register 1 */
#define S1DREG_PANEL_TYPE		0x0030	/* Panel Type Register */
#define S1DREG_MOD_RATE			0x0031	/* MOD Rate Register */
#define S1DREG_LCD_DISP_HWIDTH		0x0032	/* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */
#define S1DREG_LCD_NDISP_HPER		0x0034	/* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */
#define S1DREG_TFT_FPLINE_START		0x0035	/* TFT FPLINE Start Position Register */
#define S1DREG_TFT_FPLINE_PWIDTH	0x0036	/* TFT FPLINE Pulse Width Register. */
#define S1DREG_LCD_DISP_VHEIGHT0	0x0038	/* LCD Vertical Display Height Register 0 */
#define S1DREG_LCD_DISP_VHEIGHT1	0x0039	/* LCD Vertical Display Height Register 1 */
#define S1DREG_LCD_NDISP_VPER		0x003A	/* LCD Vertical Non-Display Period Register: (val)+1=NDlines */
#define S1DREG_TFT_FPFRAME_START	0x003B	/* TFT FPFRAME Start Position Register */
#define S1DREG_TFT_FPFRAME_PWIDTH	0x003C	/* TFT FPFRAME Pulse Width Register */
#define S1DREG_LCD_DISP_MODE		0x0040	/* LCD Display Mode Register */
#define S1DREG_LCD_MISC			0x0041	/* LCD Miscellaneous Register */
#define S1DREG_LCD_DISP_START0		0x0042	/* LCD Display Start Address Register 0 */
#define S1DREG_LCD_DISP_START1		0x0043	/* LCD Display Start Address Register 1 */
#define S1DREG_LCD_DISP_START2		0x0044	/* LCD Display Start Address Register 2 */
#define S1DREG_LCD_MEM_OFF0		0x0046	/* LCD Memory Address Offset Register 0 */
#define S1DREG_LCD_MEM_OFF1		0x0047	/* LCD Memory Address Offset Register 1 */
#define S1DREG_LCD_PIX_PAN		0x0048	/* LCD Pixel Panning Register */
#define S1DREG_LCD_DISP_FIFO_HTC	0x004A	/* LCD Display FIFO High Threshold Control Register */
#define S1DREG_LCD_DISP_FIFO_LTC	0x004B	/* LCD Display FIFO Low Threshold Control Register */
#define S1DREG_CRT_DISP_HWIDTH		0x0050	/* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */
#define S1DREG_CRT_NDISP_HPER		0x0052	/* CRT/TV Horizontal Non-Display Period Register */
#define S1DREG_CRT_HRTC_START		0x0053	/* CRT/TV HRTC Start Position Register */
#define S1DREG_CRT_HRTC_PWIDTH		0x0054	/* CRT/TV HRTC Pulse Width Register */
#define S1DREG_CRT_DISP_VHEIGHT0	0x0056	/* C