0 " l4( (  fD- _o # SPDX-License-Identifier: GPL-2.0-only config SH_INTC bool select IRQ_DOMAIN if SH_INTC comment "Interrupt controller options" config INTC_USERIMASK bool "Userspace interrupt masking support" depends on (SUPERH && CPU_SH4A) || COMPILE_TEST help This enables support for hardware-assisted userspace hardirq masking. SH-4A and newer interrupt blocks all support a special shadowed page with all non-masking registers obscured when mapped in to userspace. This is primarily for use by userspace device drivers that are using special priority levels. If in doubt, say N. config INTC_BALANCING bool "Hardware IRQ balancing support" depends on SMP && SUPERH && CPU_SHX3 help This enables support for IRQ auto-distribution mode on SH-X3 SMP parts. All of the balancing and CPU wakeup decisions are taken care of automatically by hardware for distributed vectors. If in doubt, say N. config INTC_MAPPING_DEBUG bool "Expose IRQ to per-controller id mapping via debugfs" depends on DEBUG_FS help This will create a debugfs entry for showing the relationship between system IRQs and the per-controller id tables. If in doubt, say N. endif  _I|+/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __DTS_MARVELL_PXA168_CLOCK_H #define __DTS_MARVELL_PXA168_CLOCK_H /* fixed clocks and plls */ #define PXA168_CLK_CLK32 1 #define PXA168_CLK_VCTCXO 2 #define PXA168_CLK_PLL1 3 #define PXA168_CLK_PLL1_2 8 #define PXA168_CLK_PLL1_4 9 #define PXA168_CLK_PLL1_8 10 #define PXA168_CLK_PLL1_16 11 #define PXA168_CLK_PLL1_6 12 #define PXA168_CLK_PLL1_12 13 #define PXA168_CLK_PLL1_24 14 #define PXA168_CLK_PLL1_48 15 #define PXA168_CLK_PLL1_96 16 #define PXA168_CLK_PLL1_13 17 #define PXA168_CLK_PLL1_13_1_5 18 #define PXA168_CLK_PLL1_2_1_5 19 #define PXA168_CLK_PLL1_3_16 20 #define PXA168_CLK_PLL1_192 21 #define PXA168_CLK_UART_PLL 27 #define PXA168_CLK_USB_PLL 28 /* apb periphrals */ #define PXA168_CLK_TWSI0 60 #define PXA168_CLK_TWSI1 61 #define PXA168_CLK_TWSI2 62 #define PXA168_CLK_TWSI3 63 #define PXA168_CLK_GPIO 64 #define PXA168_CLK_KPC 65 #define PXA168_CLK_RTC 66 #define PXA168_CLK_PWM0 67 #define PXA168_CLK_PWM1 68 #define PXA168_CLK_PWM2 69 #define PXA168_CLK_PWM3 70 #define PXA168_CLK_UART0 71 #define PXA168_CLK_UART1 72 #define PXA168_CLK_UART2 73 #define PXA168_CLK_SSP0 74 #define PXA168_CLK_SSP1 75 #define PXA168_CLK_SSP2 76 #define PXA168_CLK_SSP3 77 #define PXA168_CLK_SSP4 78 #define PXA168_CLK_TIMER 79 /* axi periphrals */ #define PXA168_CLK_DFC 100 #define PXA168_CLK_SDH0 101 #define PXA168_CLK_SDH1 102 #define PXA168_CLK_SDH2 103 #define PXA168_CLK_USB 104 #define PXA168_CLK_SPH 105 #define PXA168_CLK_DISP0 106 #define PXA168_CLK_CCIC0 107 #define PXA168_CLK_CCIC0_PHY 108 #define PXA168_CLK_CCIC0_SPHY 109 #define PXA168_NR_CLKS 200 #endif File not found.   e9 b/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause */ /* Authors: Bernard Metzler */ /* Copyright (c) 2008-2019, IBM Corporation */ #ifndef _SIW_USER_H #define _SIW_USER_H #include #define SIW_NODE_DESC_COMMON "Software iWARP stack" #define SIW_ABI_VERSION 1 #define SIW_MAX_SGE 6 #define SIW_UOBJ_MAX_KEY 0x08FFFF #define SIW_INVAL_UOBJ_KEY (SIW_UOBJ_MAX_KEY + 1) struct siw_uresp_create_cq { __u32 cq_id; __u32 num_cqe; __aligned_u64 cq_key; }; struct siw_uresp_create_qp { __u32 qp_id; __u32 num_sqe; __u32 num_rqe; __u32 pad; __aligned_u64 sq_key; __aligned_u64 rq_key; }; struct siw_ureq_reg_mr { __u8 stag_key; __u8 reserved[3]; __u32 pad; }; struct siw_uresp_reg_mr { __u32 stag; __u32 pad; }; struct siw_uresp_create_srq { __u32 num_rqe; __u32 pad; __aligned_u64 srq_key; }; struct siw_uresp_alloc_ctx { __u32 dev_id; __u32 pad; }; enum siw_opcode { SIW_OP_WRITE, SIW_OP_READ, SIW_OP_READ_LOCAL_INV, SIW_OP_SEND, SIW_OP_SEND_WITH_IMM