0 *l4( (  fB- _I|+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ /* Copyright (c) 2018 Mellanox Technologies. */ #ifndef MLX5_CORE_EQ_H #define MLX5_CORE_EQ_H #define MLX5_NUM_CMD_EQE (32) #define MLX5_NUM_ASYNC_EQE (0x1000) #define MLX5_NUM_SPARE_EQE (0x80) struct mlx5_eq; struct mlx5_irq; struct mlx5_core_dev; struct mlx5_eq_param { int nent; u64 mask[4]; struct mlx5_irq *irq; }; struct mlx5_eq * mlx5_eq_create_generic(struct mlx5_core_dev *dev, struct mlx5_eq_param *param); int mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq); int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq, struct notifier_block *nb); void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq, struct notifier_block *nb); struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc); void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm); /* The HCA will think the queue has overflowed if we * don't tell it we've been processing events. We * create EQs with MLX5_NUM_SPARE_EQE extra entries, * so we must update our consumer index at * least that often. * * mlx5_eq_update_cc must be called on every EQE @EQ irq handler */ static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) { if (unlikely(cc >= MLX5_NUM_SPARE_EQE)) { mlx5_eq_update_ci(eq, cc, 0); cc = 0; } return cc; } struct mlx5_nb { struct notifier_block nb; u8 event_type; }; #define mlx5_nb_cof(ptr, type, member) \ (container_of(container_of(ptr, struct mlx5_nb, nb), type, member)) #define MLX5_NB_INIT(name, handler, event) do { \ (name)->nb.notifier_call = handler; \ (name)->event_type = MLX5_EVENT_TYPE_##event; \ } while (0) #endif /* MLX5_CORE_EQ_H */  0  }C$/* SPDX-License-Identifier: GPL-2.0 */ /* * OMAP Smartreflex Defines and Routines * * Author: Thara Gopinath * * Copyright (C) 2010 Texas Instruments, Inc. * Thara Gopinath * * Copyright (C) 2008 Nokia Corporation * Kalle Jokiniemi * * Copyright (C) 2007 Texas Instruments, Inc. * Lesly A M */ #ifndef __POWER_SMARTREFLEX_H #define __POWER_SMARTREFLEX_H #include #include #include #include /* * Different Smartreflex IPs version. The v1 is the 65nm version used in * OMAP3430. The v2 is the update for the 45nm version of the IP * used in OMAP3630 and OMAP4430 */ #define SR_TYPE_V1 1 #define SR_TYPE_V2 2 /* SMART REFLEX REG ADDRESS OFFSET */ #define SRCONFIG 0x00 #define SRSTATUS 0x04 #define SENVAL 0x08 #define SENMIN 0x0C #define SENMAX 0x10 #define SENAVG 0x14 #define AVGWEIGHT 0x18 #define NVALUERECIPROCAL 0x1c #define SENERROR_V1 0x20 #define ERRCONFIG_V1 0x24 #define IRQ_EOI 0x20 #define IRQSTATUS_RAW 0x24 #define IRQSTATUS 0x28 #define IRQENABLE_SET 0x2C #define IRQENABLE_CLR 0x30 #define SENERROR_V2 0x34 #define ERRCONFIG_V2 0x38 /* Bit/Shift Positions */ /* SRCONFIG */ #define SRCONFIG_ACCUMDATA_SHIFT 22 #define SRCONFIG_SRCLKLENGTH_SHIFT 12 #define SRCONFIG_SENNENABLE_V1_SHIFT 5 #define SRCONFIG_SENPENABLE_V1_SHIFT 3 #define SRCONFIG_SENNENABLE_V2_SHIFT 1 #define SRCONFIG_SENPENABLE_V2_SHIFT 0 #define SRCONFIG_CLKCTRL_SHIFT 0 #define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22) #define SRCONFIG_SRENABLE BIT(11) #define SRCONFIG_SENENABLE BIT(10) #define SRCONFIG_ERRGEN_EN BIT(9) #define SRCONFIG_MINMAXAVG_EN BIT(8) #define SRCONFIG_DELAYCTRL BIT(2) /* AVGWEIGHT */ #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2 #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0 /* NVALUERECIPROCAL */ #define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 #define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 #define NVALUERECIPROCAL_RNSENP_SHIFT 8 #define NVALUERECIPROCAL_RNSENN_SHIFT 0 /* ERRCONFIG */ #define ERRCONFIG_ERRWEIGHT_SHIFT 16 #define ERRCONFIG_ERRMAXLIMIT_SHIFT 8 #define ERRCONFIG_ERRMINLIMIT_SHIFT 0 #define SR_ERRWEIGHT_MASK (0x07 << 16)