0 ?am_J*j"TfqTţ?File not found. A dȾ?A/* SPDX-License-Identifier: GPL-2.0-only */ /* * VMware VMCI Driver * * Copyright (C) 2012 VMware, Inc. All rights reserved. */ #ifndef _VMW_VMCI_DEF_H_ #define _VMW_VMCI_DEF_H_ #include #include /* Register offsets. */ #define VMCI_STATUS_ADDR 0x00 #define VMCI_CONTROL_ADDR 0x04 #define VMCI_ICR_ADDR 0x08 #define VMCI_IMR_ADDR 0x0c #define VMCI_DATA_OUT_ADDR 0x10 #define VMCI_DATA_IN_ADDR 0x14 #define VMCI_CAPS_ADDR 0x18 #define VMCI_RESULT_LOW_ADDR 0x1c #define VMCI_RESULT_HIGH_ADDR 0x20 #define VMCI_DATA_OUT_LOW_ADDR 0x24 #define VMCI_DATA_OUT_HIGH_ADDR 0x28 #define VMCI_DATA_IN_LOW_ADDR 0x2c #define VMCI_DATA_IN_HIGH_ADDR 0x30 #define VMCI_GUEST_PAGE_SHIFT 0x34 /* Max number of devices. */ #define VMCI_MAX_DEVICES 1 /* Status register bits. */ #define VMCI_STATUS_INT_ON BIT(0) /* Control register bits. */ #define VMCI_CONTROL_RESET BIT(0) #define VMCI_CONTROL_INT_ENABLE BIT(1) #define VMCI_CONTROL_INT_DISABLE BIT(2) /* Capabilities register bits. */ #define VMCI_CAPS_HYPERCALL BIT(0) #define VMCI_CAPS_GUESTCALL BIT(1) #define VMCI_CAPS_DATAGRAM BIT(2) #define VMCI_CAPS_NOTIFICATIONS BIT(3) #define VMCI_CAPS_PPN64 BIT(4) #define VMCI_CAPS_DMA_DATAGRAM BIT(5) /* Interrupt Cause register bits. */ #define VMCI_ICR_DATAGRAM BIT(0) #define VMCI_ICR_NOTIFICATION BIT(1) #define VMCI_ICR_DMA_DATAGRAM BIT(2) /* Interrupt Mask register bits. */ #define VMCI_IMR_DATAGRAM BIT(0) #define VMCI_IMR_NOTIFICATION BIT(1) #define VMCI_IMR_DMA_DATAGRAM BIT(2) /* * Maximum MSI/MSI-X interrupt vectors in the device. * If VMCI_CAPS_DMA_DATAGRAM is supported by the device, * VMCI_MAX_INTRS_DMA_DATAGRAM vectors are available, * otherwise only VMCI_MAX_INTRS_NOTIFICATION. */ #define VMCI_MAX_INTRS_NOTIFICATION 2 #define VMCI_MAX_INTRS_DMA_DATAGRAM 3 #define VMCI_MAX_INTRS VMCI_MAX_INTRS_DMA_DATAGRAM /* * Supported interrupt vectors. There is one for each ICR value above, * but here they indicate the position in the vector array/message ID. */ enum { VMCI_INTR_DATAGRAM = 0, VMCI_INTR_NOTIFICATION = 1, VMCI_INTR_DMA_DATAGRAM = 2, }; /* * A single VMCI device has an upper limit of 128MB on the amount of * memory that can be used for queue pairs. Since each queue pair * consists of at least two pages, the memory limit also dictates the * number of queue pairs a guest can create. */ #define VMCI_MAX_GUEST_QP_MEMORY ((size_t)(128 * 1024 * 1024)) #define VMCI_MAX_GUEST_QP_COUNT (VMCI_MAX_GUEST_QP_MEMORY / PAGE_SIZE / 2) /* * There can be at most PAGE_SIZE doorbells since there is one doorbell * per byte in the doorbell bitmap page. */ #define VMCI_MAX_GUEST_DOORBELL_COUNT PAGE_SIZE /* * Queues with pre-mapped data pages must be small, so that we don't pin * too much kernel memory (especially on vmkernel). We limit a queuepair to * 32 KB, or 16 KB per queue for symmetrical pairs. */ #define VMCI_MAX_PINNED_QP_MEMORY ((size_t)(32 * 1024)) /* * The version of the VMCI device that supports MMIO access to registers * requests 256KB for BAR1 whereas the version of VMCI that supports * MSI/MSI-X only requests 8KB. The layout of the larger 256KB region is: * - the first 128KB are used for MSI/MSI-X. * - the following 64KB are used for MMIO register access. * - the remaining 64KB are unused. */ #define VMCI_WITH_MMIO_ACCESS_BAR_SIZE ((size_t)(256 * 1024)) #define VMCI_MMIO_ACCESS_OFFSET ((size_t)(128 * 1024)) #define VMCI_MMIO_ACCESS_SIZE ((size_t)(64 * 1024)) /* * For VMCI devices supporting the VMCI_CAPS_DMA_DATAGRAM capability, the * sending and receiving of datagrams can be performed using DMA to/from * a driver allocated buffer. * Sending and receiving will be handled as follows: * - when sending datagrams, the driver initializes the buffer where the * data part will refer to the outgoing VMCI datagram, sets the busy flag * to