MAJOR=4
MINOR=19
DEVNAME=tty19
  "   ˆl–Ü4ý( ©³( 	Å€fàD¦-ÿÁƒ!À¿ '    # SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Linux SuperH-specific parts of the memory manager.
#

obj-y			:= alignment.o cache.o init.o consistent.o mmap.o

cacheops-$(CONFIG_CPU_J2)		:= cache-j2.o
cacheops-$(CONFIG_CPU_SUBTYPE_SH7619)	:= cache-sh2.o
cacheops-$(CONFIG_CPU_SH2A)		:= cache-sh2a.o
cacheops-$(CONFIG_CPU_SH3)		:= cache-sh3.o
cacheops-$(CONFIG_CPU_SH4)		:= cache-sh4.o flush-sh4.o
cacheops-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o
cacheops-$(CONFIG_CPU_SHX3)		+= cache-shx3.o

obj-y			+= $(cacheops-y)

mmu-y			:= nommu.o extable_32.o
mmu-$(CONFIG_MMU)	:= extable_32.o fault.o ioremap.o kmap.o \
			   pgtable.o tlbex_32.o tlbflush_32.o

obj-y			+= $(mmu-y)

debugfs-y			:= asids-debugfs.o
ifndef CONFIG_CACHE_OFF
debugfs-$(CONFIG_CPU_SH4)	+= cache-debugfs.o
endif

ifdef CONFIG_MMU
debugfs-$(CONFIG_CPU_SH4)	+= tlb-debugfs.o
tlb-$(CONFIG_CPU_SH3)		:= tlb-sh3.o
tlb-$(CONFIG_CPU_SH4)		:= tlb-sh4.o tlb-urb.o
tlb-$(CONFIG_CPU_HAS_PTEAEX)	:= tlb-pteaex.o tlb-urb.o
obj-y				+= $(tlb-y)
endif

obj-$(CONFIG_DEBUG_FS)		+= $(debugfs-y)
obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
obj-$(CONFIG_PMB)		+= pmb.o
obj-$(CONFIG_NUMA)		+= numa.o
obj-$(CONFIG_IOREMAP_FIXED)	+= ioremap_fixed.o
obj-$(CONFIG_UNCACHED_MAPPING)	+= uncached.o
obj-$(CONFIG_HAVE_SRAM_POOL)	+= sram.o

GCOV_PROFILE_pmb.o := n
  *   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿÂƒyöE_†I|¥+ÂÁ "ä    /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 * 	Author: Tomasz Figa <t.figa@samsung.com>
 *
 * Device Tree binding constants for Samsung Exynos3250 clock controllers.
 */

#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H

/*
 * Let each exported clock get a unique index, which is used on DT-enabled
 * platforms to lookup the clock from a clock specifier. These indices are
 * therefore considered an ABI and so must not be changed. This implies
 * that new clocks should be added either in free spaces between clock groups
 * or at the end.
 */


/*
 * Main CMU
 */

#define CLK_OSCSEL			1
#define CLK_FIN_PLL			2
#define CLK_FOUT_APLL			3
#define CLK_FOUT_VPLL			4
#define CLK_FOUT_UPLL			5
#define CLK_FOUT_MPLL			6
#define CLK_ARM_CLK			7

/* Muxes */
#define CLK_MOUT_MPLL_USER_L		16
#define CLK_MOUT_GDL			17
#define CLK_MOUT_MPLL_USER_R		18
#define CLK_MOUT_GDR			19
#define CLK_MOUT_EBI			20
#define CLK_MOUT_ACLK_200		21
#define CLK_MOUT_ACLK_160		22
#define CLK_MOUT_ACLK_100		23
#define CLK_MOUT_ACLK_266_1		24
#define CLK_MOUT_ACLK_266_0		25
#define CLK_MOUT_ACLK_266		26
#define CLK_MOUT_VPLL			27
#define CLK_MOUT_EPLL_USER		28
#define CLK_MOUT_EBI_1			29
#define CLK_MOUT_UPLL			30
#define CLK_MOUT_ACLK_400_MCUISP_SUB	31
#define CLK_MOUT_MPLL			32
#define CLK_MOUT_ACLK_400_MCUISP	33
#define CLK_MOUT_VPLLSRC		34
#define CLK_MOUT_CAM1			35
#define CLK_MOUT_CAM_BLK		36
#define CLK_MOUT_MFC			37
#define CLK_MOUT_MFC_1			38
#define CLK_MOUT_MFC_0			39
#define CLK_MOUT_G3D			40
#define CLK_MOUT_G3D_1			41
#define CLK_MOUT_G3D_0			42
#define CLK_MOUT_MIPI0			43
#define CLK_MOUT_FIMD0			44
#define CLK_MOUT_UART_ISP		45
#define CLK_MOUT_SPI1_ISP		46
#define CLK_MOUT_SPI0_ISP		47
#define CLK_MOUT_TSADC			48
#define CLK_MOUT_MMC1			49
#define CLK_MOUT_MMC0			50
#define CLK_MOUT_UART1			51
#define CLK_MOUT_UART0			52
#define CLK_MOUT_SPI1			53
#define CLK_MOUT_SPI0			54
#define CLK_MOUT_AUDIO			55
#define CLK_MOUT_MPLL_USER_C		56
#define CLK_MOUT_HPM			57
#define CLK_MOUT_CORE			58
#define CLK_MOUT_APLL			59
#define CLK_MOUT_ACLK_266_SUB		60
#define CLK_MOUT_UART2			61
#define CLK_MOUT_MMC2			62

/* Dividers */
#define CLK_DIV_GPL			64
#define CLK_DIV_GDL			65
#define CLK_DIV_GPR			66
#define CLK_DIV_GDR			67
#define CLK_DIV_MPLL_PRE		68
#define CLK_DIV_ACLK_400_MCUISP		69
#define CLK_DIV_EBI			70
#define CLK_DIV_ACLK_200		71
#define CLK_DIV_ACLK_160		72
#define CLK_DIV_ACLK_100		73
#define CLK_DIV_ACLK_266		74
#define CLK_DIV_CAM1			75
#define CLK_DIV_CAM_BLK			76
#define CLK_DIV_MFC			77
#defi