MAJOR=4 MINOR=8 DEVNAME=tty8 ˆÁÀ „ -¾Ï¿ÂÄ5/* SPDX-License-Identifier: GPL-2.0 */ /* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $ * linux/drivers/video/aty128.h * Register definitions for ATI Rage128 boards * * Anthony Tong , 1999 * Brad Douglas , 2000 */ #ifndef REG_RAGE128_H #define REG_RAGE128_H #define CLOCK_CNTL_INDEX 0x0008 #define CLOCK_CNTL_DATA 0x000c #define BIOS_0_SCRATCH 0x0010 #define BUS_CNTL 0x0030 #define BUS_CNTL1 0x0034 #define GEN_INT_CNTL 0x0040 #define CRTC_GEN_CNTL 0x0050 #define CRTC_EXT_CNTL 0x0054 #define DAC_CNTL 0x0058 #define I2C_CNTL_1 0x0094 #define PALETTE_INDEX 0x00b0 #define PALETTE_DATA 0x00b4 #define CNFG_CNTL 0x00e0 #define GEN_RESET_CNTL 0x00f0 #define CNFG_MEMSIZE 0x00f8 #define MEM_CNTL 0x0140 #define MEM_POWER_MISC 0x015c #define AGP_BASE 0x0170 #define AGP_CNTL 0x0174 #define AGP_APER_OFFSET 0x0178 #define PCI_GART_PAGE 0x017c #define PC_NGUI_MODE 0x0180 #define PC_NGUI_CTLSTAT 0x0184 #define MPP_TB_CONFIG 0x01C0 #define MPP_GP_CONFIG 0x01C8 #define VIPH_CONTROL 0x01D0 #define CRTC_H_TOTAL_DISP 0x0200 #define CRTC_H_SYNC_STRT_WID 0x0204 #define CRTC_V_TOTAL_DISP 0x0208 #define CRTC_V_SYNC_STRT_WID 0x020c #define CRTC_VLINE_CRNT_VLINE 0x0210 #define CRTC_CRNT_FRAME 0x0214 #define CRTC_GUI_TRIG_VLINE 0x0218 #define CRTC_OFFSET 0x0224 #define CRTC_OFFSET_CNTL 0x0228 #define CRTC_PITCH 0x022c #define OVR_CLR 0x0230 #define OVR_WID_LEFT_RIGHT 0x0234 #define OVR_WID_TOP_BOTTOM 0x0238 #define LVDS_GEN_CNTL 0x02d0 #define DDA_CONFIG 0x02e0 #define DDA_ON_OFF 0x02e4 #define VGA_DDA_CONFIG 0x02e8 #define VGA_DDA_ON_OFF 0x02ec #define CRTC2_H_TOTAL_DISP 0x0300 #define CRTC2_H_SYNC_STRT_WID 0x0304 #define CRTC2_V_TOTAL_DISP 0x0308 #define CRTC2_V_SYNC_STRT_WID 0x030c #define CRTC2_VLINE_CRNT_VLINE 0x0310 #define CRTC2_CRNT_FRAME 0x0314 #define CRTC2_GUI_TRIG_VLINE 0x0318 #define CRTC2_OFFSET 0x0324 #define CRTC2_OFFSET_CNTL 0x0328 #define CRTC2_PITCH 0x032c #define DDA2_CONFIG 0x03e0 #define DDA2_ON_OFF 0x03e4 #define CRTC2_GEN_CNTL 0x03f8 #define CRTC2_STATUS 0x03fc #define OV0_SCALE_CNTL 0x0420 #define SUBPIC_CNTL 0x0540 #define PM4_BUFFER_OFFSET 0x0700 #define PM4_BUFFER_CNTL 0x0704 #define PM4_BUFFER_WM_CNTL 0x0708 #define PM4_BUFFER_DL_RPTR_ADDR 0x070c #define PM4_BUFFER_DL_RPTR 0x0710 #define PM4_BUFFER_DL_WPTR 0x0714 #define PM4_VC_FPU_SETUP 0x071c #define PM4_FPU_CNTL 0x0720 #define PM4_VC_FORMAT 0x0724 #define PM4_VC_CNTL 0x0728 #define PM4_VC_I01 0x072c #define PM4_VC_VLOFF 0x0730 #define PM4_VC_VLSIZE 0x0734 #define PM4_IW_INDOFF 0x0738 #define PM4_IW_INDSIZE 0x073c #define PM4_FPU_FPX0 0x0740 #define PM4_FPU_FPY0 0x0744 #define PM4_FPU_FPX1 0x0748 #define PM4_FPU_FPY1 0x074c #define PM4_FPU_FPX2 0x0750 #define PM4_FPU_FPY2 0x0754 #define PM4_FPU_FPY3 0x0758 #define PM4_FPU_FPY4 0x075c #define PM4_FPU_FPY5 0x0760 #define PM4_FPU_FPY6 0x0764 #define PM4_FPU_FPR 0x0768 #define PM4_FPU_FPG 0x076c #define PM4_FPU_FPB 0x0770 #define PM4_FPU_FPA 0x0774 #define PM4_FPU_INTXY0 0x0780 #define PM4_FPU_INTXY1 0x0784 #define PM4_FPU_INTXY2 0x0788 #define PM4_FPU_INTARGB 0x078c #define PM4_FPU_FPTWICEAREA 0x0790 #define PM4_FPU_DMAJOR01 0x0794 #define PM4_FPU_DMAJOR12 0x0798 #define PM4_FPU_DMAJOR02 0x079c #define PM4_FPU_STAT 0x07a0 #define PM4_STAT 0x07b8 #define PM4_TEST_CNTL 0x07d0 #define PM4_MICROCODE_ADDR 0x07d4 #define PM4_MICROCODE_RADDR 0x07d8 #define PM4_MICROCODE_DATAH 0x07dc #define PM4_MICROCODE_DATAL 0x07e0 #define PM4_CMDFIFO_ADDR 0x07e4 #define PM4_CMDFIFO_DATAH 0x07e8 #define PM4_CMDFIFO_DATAL 0x07ec #define PM4_BUFFER_ADDR 0x07f0 #define PM4_BUFFER_DATAH 0x07f4 #define PM4_BUFFER_DATAL 0x07f8 #define PM4_MICRO_CNTL 0x07fc #define CAP0_TRIG_CNTL 0x0950 #define CAP1_TRIG_CNTL 0x09c0 /****************************