auto *l4( (  fB- 747_I|+/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Authenc: Simple AEAD wrapper for IPsec * * Copyright (c) 2007 Herbert Xu */ #ifndef _CRYPTO_AUTHENC_H #define _CRYPTO_AUTHENC_H #include enum { CRYPTO_AUTHENC_KEYA_UNSPEC, CRYPTO_AUTHENC_KEYA_PARAM, }; struct crypto_authenc_key_param { __be32 enckeylen; }; struct crypto_authenc_keys { const u8 *authkey; const u8 *enckey; unsigned int authkeylen; unsigned int enckeylen; }; int crypto_authenc_extractkeys(struct crypto_authenc_keys *keys, const u8 *key, unsigned int keylen); int crypto_krb5enc_extractkeys(struct crypto_authenc_keys *keys, const u8 *key, unsigned int keylen); #endif /* _CRYPTO_AUTHENC_H */  }%K/* SPDX-License-Identifier: GPL-2.0+ */ /* * Internal header file for Samsung S3C2410 serial ports (UART0-2) * * Copyright (C) 2002 Shane Nay (shane@minirl.com) * * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk) * * Adapted from: * * Internal header file for MX1ADS serial ports (UART1 & 2) * * Copyright (C) 2002 Shane Nay (shane@minirl.com) */ #ifndef __ASM_ARM_REGS_SERIAL_H #define __ASM_ARM_REGS_SERIAL_H #define S3C2410_URXH (0x24) #define S3C2410_UTXH (0x20) #define S3C2410_ULCON (0x00) #define S3C2410_UCON (0x04) #define S3C2410_UFCON (0x08) #define S3C2410_UMCON (0x0C) #define S3C2410_UBRDIV (0x28) #define S3C2410_UTRSTAT (0x10) #define S3C2410_UERSTAT (0x14) #define S3C2410_UFSTAT (0x18) #define S3C2410_UMSTAT (0x1C) #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) #define S3C2410_LCON_CS5 (0x0) #define S3C2410_LCON_CS6 (0x1) #define S3C2410_LCON_CS7 (0x2) #define S3C2410_LCON_CS8 (0x3) #define S3C2410_LCON_CSMASK (0x3) #define S3C2410_LCON_PNONE (0x0) #define S3C2410_LCON_PEVEN (0x5 << 3) #define S3C2410_LCON_PODD (0x4 << 3) #define S3C2410_LCON_PMASK (0x7 << 3) #define S3C2410_LCON_STOPB (1<<2) #define S3C2410_LCON_IRM (1<<6) #define S3C2440_UCON_CLKMASK (3<<10) #define S3C2440_UCON_CLKSHIFT (10) #define S3C2440_UCON_PCLK (0<<10) #define S3C2440_UCON_UCLK (1<<10) #define S3C2440_UCON_PCLK2 (2<<10) #define S3C2440_UCON_FCLK (3<<10) #define S3C2443_UCON_EPLL (3<<10) #define S3C6400_UCON_CLKMASK (3<<10) #define S3C6400_UCON_CLKSHIFT (10) #define S3C6400_UCON_PCLK (0<<10) #define S3C6400_UCON_PCLK2 (2<<10) #define S3C6400_UCON_UCLK0 (1<<10) #define S3C6400_UCON_UCLK1 (3<<10) #define S3C2440_UCON2_FCLK_EN (1<<15) #define S3C2440_UCON0_DIVMASK (15 << 12) #define S3C2440_UCON1_DIVMASK (15 << 12) #define S3C2440_UCON2_DIVMASK (7 << 12) #define S3C2440_UCON_DIVSHIFT (12) #define S3C2412_UCON_CLKMASK (3<<10) #define S3C2412_UCON_CLKSHIFT (10) #define S3C2412_UCON_UCLK (1<<10) #define S3C2412_UCON_USYSCLK (3<<10) #define S3C2412_UCON_PCLK (0<<10) #define S3C2412_UCON_PCLK2 (2<<10) #define S3C2410_UCON_CLKMASK (1 << 10) #define S3C2410_UCON_CLKSHIFT (10) #define S3C2410_UCON_UCLK (1<<10) #define S3C2410_UCON_SBREAK (1<<4) #define S3C2410_UCON_TXILEVEL (1<<9) #define S3C2410_UCON_RXILEVEL (1<<8) #define S3C2410_UCON_TXIRQMODE (1<<2) #define S3C2410_UCON_RXIRQMODE (1<<0) #define S3C2410_UCON_RXFIFO_TOI (1<<7) #define S3C2443_UCON_RXERR_IRQEN (1<<6) #define S3C2410_UCON_LOOPBACK (1<<5) #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI) #define S3C64XX_UCON_TXBURST_1 (0<<20) #define S3C64XX_UCON_TXBURST_4 (1<<20) #define S3C64XX_UCON_TXBURST_8 (2<<20) #define S3C64XX_UCON_TXBURST_16 (3<<20) #define S3C64XX_UCON_TXBURST_MASK (0xf<<20) #define S3C64XX_UCON_RXBURST_1 (0<<16) #define S3C64XX_UCON_RXBURST_4 (1<<16) #define S3C64XX_UCON_RXBURST_8 (2<<16) #define S3C64XX_UCON_RXBURST_16 (3<<16) #define S3C64XX_UCON_RXBURST_MASK (0xf<<16) #def