auto ˆÉÈ „`qŸÇÂÅ?÷/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Freescale Integrated Flash Controller * * Copyright 2011 Freescale Semiconductor, Inc * * Author: Dipen Dudhat */ #ifndef __ASM_FSL_IFC_H #define __ASM_FSL_IFC_H #include #include #include #include #include /* * The actual number of banks implemented depends on the IFC version * - IFC version 1.0 implements 4 banks. * - IFC version 1.1 onward implements 8 banks. */ #define FSL_IFC_BANK_COUNT 8 #define FSL_IFC_VERSION_MASK 0x0F0F0000 #define FSL_IFC_VERSION_1_0_0 0x01000000 #define FSL_IFC_VERSION_1_1_0 0x01010000 #define FSL_IFC_VERSION_2_0_0 0x02000000 #define PGOFFSET_64K (64*1024) #define PGOFFSET_4K (4*1024) /* * CSPR - Chip Select Property Register */ #define CSPR_BA 0xFFFF0000 #define CSPR_BA_SHIFT 16 #define CSPR_PORT_SIZE 0x00000180 #define CSPR_PORT_SIZE_SHIFT 7 /* Port Size 8 bit */ #define CSPR_PORT_SIZE_8 0x00000080 /* Port Size 16 bit */ #define CSPR_PORT_SIZE_16 0x00000100 /* Port Size 32 bit */ #define CSPR_PORT_SIZE_32 0x00000180 /* Write Protect */ #define CSPR_WP 0x00000040 #define CSPR_WP_SHIFT 6 /* Machine Select */ #define CSPR_MSEL 0x00000006 #define CSPR_MSEL_SHIFT 1 /* NOR */ #define CSPR_MSEL_NOR 0x00000000 /* NAND */ #define CSPR_MSEL_NAND 0x00000002 /* GPCM */ #define CSPR_MSEL_GPCM 0x00000004 /* Bank Valid */ #define CSPR_V 0x00000001 #define CSPR_V_SHIFT 0 /* * Address Mask Register */ #define IFC_AMASK_MASK 0xFFFF0000 #define IFC_AMASK_SHIFT 16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ (__ilog2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine */ /* Enable ECC Encoder */ #define CSOR_NAND_ECC_ENC_EN 0x80000000 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 /* 4 bit correction per 520 Byte sector */ #define CSOR_NAND_ECC_MODE_4 0x00000000 /* 8 bit correction per 528 Byte sector */ #define CSOR_NAND_ECC_MODE_8 0x10000000 /* Enable ECC Decoder */ #define CSOR_NAND_ECC_DEC_EN 0x04000000 /* Row Address Length */ #define CSOR_NAND_RAL_MASK 0x01800000 #define CSOR_NAND_RAL_SHIFT 20 #define CSOR_NAND_RAL_1 0x00000000 #define CSOR_NAND_RAL_2 0x00800000 #define CSOR_NAND_RAL_3 0x01000000 #define CSOR_NAND_RAL_4 0x01800000 /* Page Size 512b, 2k, 4k */ #define CSOR_NAND_PGS_MASK 0x00180000 #define CSOR_NAND_PGS_SHIFT 16 #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 #define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 #define CSOR_NAND_SPRZ_16 0x00000000 #define CSOR_NAND_SPRZ_64 0x00002000 #define CSOR_NAND_SPRZ_128 0x00004000 #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK 0x0000001C #define CSOR_NAND_TRHZ_SHIFT 2 #define CSOR_NAND_TRHZ_20 0x00000000 #define CSOR_NAND_TRHZ_40 0x00000004 #define CSOR_NAND_TRHZ_60 0x00000008 #define CSOR_NAND_TRHZ_80 0x0000000C #define CSOR_NAND_TRHZ_100 0x00000010 /* Buffer control disable */ #define CSOR_NAND_BCTLD 0x00000001 /* * Chip Select Option Register - NOR Flash Mode */ /* Enable Address shift Mode */ #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 /* Page Read Enable from NOR device */ #define CSOR_NOR_PGRD_EN 0x10000000 /* AVD Toggle Enable during Burst Program */ #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 /* Address Data Multiplexing Shift */ #define CSOR_NOR_ADM_MASK 0x0003E000 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) /* Type of the NOR device hooked */ #define CSOR_NOR_NOR_MODE_AYSNC_