suspended =li~ Je8q 1h 0 ? 354b?/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __A_OUT_GNU_H__ #define __A_OUT_GNU_H__ #include #ifndef __ASSEMBLY__ #ifdef linux #include #if defined(__i386__) || defined(__mc68000__) #else #ifndef SEGMENT_SIZE #define SEGMENT_SIZE PAGE_SIZE #endif #endif #endif #endif /*__ASSEMBLY__ */ #endif /* __A_OUT_GNU_H__ */ AAFile not found. C uC/* SPDX-License-Identifier: GPL-2.0-only */ /* include/linux/amba/pl080.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks * * ARM PrimeCell PL080 DMA controller */ /* Note, there are some Samsung updates to this controller block which * make it not entierly compatible with the PL080 specification from * ARM. When in doubt, check the Samsung documentation first. * * The Samsung defines are PL080S, and add an extra control register, * the ability to move more than 2^11 counts of data and some extra * OneNAND features. */ #ifndef ASM_PL080_H #define ASM_PL080_H #define PL080_INT_STATUS (0x00) #define PL080_TC_STATUS (0x04) #define PL080_TC_CLEAR (0x08) #define PL080_ERR_STATUS (0x0C) #define PL080_ERR_CLEAR (0x10) #define PL080_RAW_TC_STATUS (0x14) #define PL080_RAW_ERR_STATUS (0x18) #define PL080_EN_CHAN (0x1c) #define PL080_SOFT_BREQ (0x20) #define PL080_SOFT_SREQ (0x24) #define PL080_SOFT_LBREQ (0x28) #define PL080_SOFT_LSREQ (0x2C) #define PL080_CONFIG (0x30) #define PL080_CONFIG_M2_BE BIT(2) #define PL080_CONFIG_M1_BE BIT(1) #define PL080_CONFIG_ENABLE BIT(0) #define PL080_SYNC (0x34) /* The Faraday Technology FTDMAC020 variant registers */ #define FTDMAC020_CH_BUSY (0x20) /* Identical to PL080_CONFIG */ #define FTDMAC020_CSR (0x24) /* Identical to PL080_SYNC */ #define FTDMAC020_SYNC (0x2C) #define FTDMAC020_REVISION (0x30) #define FTDMAC020_FEATURE (0x34) /* Per channel configuration registers */ #define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) #define PL080_CH_SRC_ADDR (0x00) #define PL080_CH_DST_ADDR (0x04) #define PL080_CH_LLI (0x08) #define PL080_CH_CONTROL (0x0C) #define PL080_CH_CONFIG (0x10) #define PL080S_CH_CONTROL2 (0x10) #define PL080S_CH_CONFIG (0x14) /* The Faraday FTDMAC020 derivative shuffles the registers around */ #define FTDMAC020_CH_CSR (0x00) #define FTDMAC020_CH_CFG (0x04) #define FTDMAC020_CH_SRC_ADDR (0x08) #define FTDMAC020_CH_DST_ADDR (0x0C) #define FTDMAC020_CH_LLP (0x10) #define FTDMAC020_CH_SIZE (0x14) #define PL080_LLI_ADDR_MASK GENMASK(31, 2) #define PL080_LLI_ADDR_SHIFT (2) #define PL080_LLI_LM_AHB2 BIT(0) #define PL080_CONTROL_TC_IRQ_EN BIT(31) #define PL080_CONTROL_PROT_MASK GENMASK(30, 28) #define PL080_CONTROL_PROT_SHIFT (28) #define PL080_CONTROL_PROT_CACHE BIT(30) #define PL080_CONTROL_PROT_BUFF BIT(29) #define PL080_CONTROL_PROT_SYS BIT(28) #define PL080_CONTROL_DST_INCR BIT(27) #define PL080_CONTROL_SRC_INCR BIT(26) #define PL080_CONTROL_DST_AHB2 BIT(25) #define PL080_CONTROL_SRC_AHB2 BIT(24) #define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21) #define PL080_CONTROL_DWIDTH_SHIFT (21) #define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18) #define PL080_CONTROL_SWIDTH_SHIFT (18) #define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15) #define PL080_CONTROL_DB_SIZE_SHIFT (15) #define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12) #define PL080_CONTROL_SB_SIZE_SHIFT (12) #define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0) #define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0) #define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) #define PL080_BSIZE_1 (0x0) #define PL080_BSIZE_4 (0x1) #define PL080_BSIZE_8 (0x2) #define PL080_BSIZE_16 (0x3) #define PL080_BSIZE_32 (0x4) #define PL080_BSIZE_64 (0x5) #define PL080_BSIZE_128 (0x6) #define PL080_BSIZE_256 (0x7) #define PL080_WIDTH_8BIT (0x0) #define PL080_WIDTH_16BIT (0x1) #define PL080_WIDTH_32BIT (0x2)