MAJOR=4
MINOR=58
DEVNAME=tty58
=
=
Index of /anon_sym/anon/sys/dev/char/4:23/subsystem/tty27/power
Index of /anon_sym/anon/sys/dev/char/4:23/subsystem/tty27/power
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u3 ?// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2010 OMICRON electronics GmbH
* Copyright 2018 NXP
*/
#ifndef __PTP_QORIQ_H__
#define __PTP_QORIQ_H__
#include
#include
#include
/*
* qoriq ptp registers
*/
struct ctrl_regs {
u32 tmr_ctrl; /* Timer control register */
u32 tmr_tevent; /* Timestamp event register */
u32 tmr_temask; /* Timer event mask register */
u32 tmr_pevent; /* Timestamp event register */
u32 tmr_pemask; /* Timer event mask register */
u32 tmr_stat; /* Timestamp status register */
u32 tmr_cnt_h; /* Timer counter high register */
u32 tmr_cnt_l; /* Timer counter low register */
u32 tmr_add; /* Timer drift compensation addend register */
u32 tmr_acc; /* Timer accumulator register */
u32 tmr_prsc; /* Timer prescale */
u8 res1[4];
u32 tmroff_h; /* Timer offset high */
u32 tmroff_l; /* Timer offset low */
};
struct alarm_regs {
u32 tmr_alarm1_h; /* Timer alarm 1 high register */
u32 tmr_alarm1_l; /* Timer alarm 1 high register */
u32 tmr_alarm2_h; /* Timer alarm 2 high register */
u32 tmr_alarm2_l; /* Timer alarm 2 high register */
};
struct fiper_regs {
u32 tmr_fiper1; /* Timer fixed period interval */
u32 tmr_fiper2; /* Timer fixed period interval */
u32 tmr_fiper3; /* Timer fixed period interval */
};
struct etts_regs {
u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
};
struct ptp_qoriq_registers {
struct ctrl_regs __iomem *ctrl_regs;
struct alarm_regs __iomem *alarm_regs;
struct fiper_regs __iomem *fiper_regs;
struct etts_regs __iomem *etts_regs;
};
/* Offset definitions for the four register groups */
#define ETSEC_CTRL_REGS_OFFSET 0x0
#define ETSEC_ALARM_REGS_OFFSET 0x40
#define ETSEC_FIPER_REGS_OFFSET 0x80
#define ETSEC_ETTS_REGS_OFFSET 0xa0
#define CTRL_REGS_OFFSET 0x80
#define ALARM_REGS_OFFSET 0xb8
#define FIPER_REGS_OFFSET 0xd0
#define ETTS_REGS_OFFSET 0xe0
/* Bit definitions for the TMR_CTRL register */
#define ALM1P (1<<31) /* Alarm1 output