MAJOR=4 MINOR=5 DEVNAME=tty5 ˆ ƒ ¢oʿȽ Index of /FSS-OZR/root/sys/dev/char/13:66/subsystem/event5/device/power

Index of /FSS-OZR/root/sys/dev/char/13:66/subsystem/event5/device/power

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 autosuspend_delay_ms 2026-10-12 01:53 4.0K 
 control 2026-10-12 01:53 4.0K 
 runtime_active_time 2026-10-12 01:53 4.0K 
 runtime_status 2026-10-12 01:53 4.0K 
 runtime_suspended_time 2026-10-12 01:53 4.0K 
"ˆl–Ðz¾””ÔD¨ ÅÝÆÙ¸Ó*bÑ¿Ç ƒh¹ÀÉ0 !ˆ¾Ç 0ÀÉ #ˆ ƒ M½ËÀɲ# Index of /anon_sym/anon/sys/dev/char/4:54/subsystem/tty61

Index of /anon_sym/anon/sys/dev/char/4:54/subsystem/tty61

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 dev 2026-10-12 01:53 4.0K 
 power/ 2026-10-12 01:53 -  
 subsystem/ 2026-10-11 21:02 -  
 uevent 2026-10-12 01:53 4.0K 
#%ˆÅÇ ƒd-³Äa–Ðz¾””ÔD¨ ÅÝÆÙ¸ÓJbÑ¿Ê Q%/* SPDX-License-Identifier: GPL-2.0-only */ /* * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...) * * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) */ #ifndef __SOC_ARC_MCIP_H #define __SOC_ARC_MCIP_H #include #define ARC_REG_MCIP_BCR 0x0d0 #define ARC_REG_MCIP_IDU_BCR 0x0D5 #define ARC_REG_GFRC_BUILD 0x0D6 #define ARC_REG_MCIP_CMD 0x600 #define ARC_REG_MCIP_WDATA 0x601 #define ARC_REG_MCIP_READBACK 0x602 struct mcip_cmd { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:8, param:16, cmd:8; #else unsigned int cmd:8, param:16, pad:8; #endif #define CMD_INTRPT_GENERATE_IRQ 0x01 #define CMD_INTRPT_GENERATE_ACK 0x02 #define CMD_INTRPT_READ_STATU