00 +l4( (  fB- D_I|+,/* SPDX-License-Identifier: GPL-2.0-only */ /* * Defines for Mobile High-Definition Link (MHL) interface * * Copyright (C) 2015, Samsung Electronics, Co., Ltd. * Andrzej Hajda * * Based on MHL driver for Android devices. * Copyright (C) 2013-2014 Silicon Image, Inc. */ #ifndef __MHL_H__ #define __MHL_H__ #include /* Device Capabilities Registers */ enum { MHL_DCAP_DEV_STATE, MHL_DCAP_MHL_VERSION, MHL_DCAP_CAT, MHL_DCAP_ADOPTER_ID_H, MHL_DCAP_ADOPTER_ID_L, MHL_DCAP_VID_LINK_MODE, MHL_DCAP_AUD_LINK_MODE, MHL_DCAP_VIDEO_TYPE, MHL_DCAP_LOG_DEV_MAP, MHL_DCAP_BANDWIDTH, MHL_DCAP_FEATURE_FLAG, MHL_DCAP_DEVICE_ID_H, MHL_DCAP_DEVICE_ID_L, MHL_DCAP_SCRATCHPAD_SIZE, MHL_DCAP_INT_STAT_SIZE, MHL_DCAP_RESERVED, MHL_DCAP_SIZE }; #define MHL_DCAP_CAT_SINK 0x01 #define MHL_DCAP_CAT_SOURCE 0x02 #define MHL_DCAP_CAT_POWER 0x10 #define MHL_DCAP_CAT_PLIM(x) ((x) << 5) #define MHL_DCAP_VID_LINK_RGB444 0x01 #define MHL_DCAP_VID_LINK_YCBCR444 0x02 #define MHL_DCAP_VID_LINK_YCBCR422 0x04 #define MHL_DCAP_VID_LINK_PPIXEL 0x08 #define MHL_DCAP_VID_LINK_ISLANDS 0x10 #define MHL_DCAP_VID_LINK_VGA 0x20 #define MHL_DCAP_VID_LINK_16BPP 0x40 #define MHL_DCAP_AUD_LINK_2CH 0x01 #define MHL_DCAP_AUD_LINK_8CH 0x02 #define MHL_DCAP_VT_GRAPHICS 0x00 #define MHL_DCAP_VT_PHOTO 0x02 #define MHL_DCAP_VT_CINEMA 0x04 #define MHL_DCAP_VT_GAMES 0x08 #define MHL_DCAP_SUPP_VT 0x80 #define MHL_DCAP_LD_DISPLAY 0x01 #define MHL_DCAP_LD_VIDEO 0x02 #define MHL_DCAP_LD_AUDIO 0x04 #define MHL_DCAP_LD_MEDIA 0x08 #define MHL_DCAP_LD_TUNER 0x10 #define MHL_DCAP_LD_RECORD 0x20 #define MHL_DCAP_LD_SPEAKER 0x40 #define MHL_DCAP_LD_GUI 0x80 #define MHL_DCAP_LD_ALL 0xFF #define MHL_DCAP_FEATURE_RCP_SUPPORT 0x01 #define MHL_DCAP_FEATURE_RAP_SUPPORT 0x02 #define MHL_DCAP_FEATURE_SP_SUPPORT 0x04 #define MHL_DCAP_FEATURE_UCP_SEND_SUPPOR 0x08 #define MHL_DCAP_FEATURE_UCP_RECV_SUPPORT 0x10 #define MHL_DCAP_FEATURE_RBP_SUPPORT 0x40 /* Extended Device Capabilities Registers */ enum { MHL_XDC_ECBUS_SPEEDS, MHL_XDC_TMDS_SPEEDS, MHL_XDC_ECBUS_ROLES, MHL_XDC_LOG_DEV_MAPX, MHL_XDC_SIZE }; #define MHL_XDC_ECBUS_S_075 0x01 #define MHL_XDC_ECBUS_S_8BIT 0x02 #define MHL_XDC_ECBUS_S_12BIT 0x04 #define MHL_XDC_ECBUS_D_150 0x10 #define MHL_XDC_ECBUS_D_8BIT 0x20 #define MHL_XDC_TMDS_000 0x00 #define MHL_XDC_TMDS_150 0x01 #define MHL_XDC_TMDS_300 0x02 #define MHL_XDC_TMDS_600 0x04 /* MHL_XDC_ECBUS_ROLES flags */ #define MHL_XDC_DEV_HOST 0x01 #define MHL_XDC_DEV_DEVICE 0x02 #define MHL_XDC_DEV_CHARGER 0x04 #define MHL_XDC_HID_HOST 0x08 #define MHL_XDC_HID_DEVICE 0x10 /* MHL_XDC_LOG_DEV_MAPX flags */ #define MHL_XDC_LD_PHONE 0x01 /* Device Status Registers */ enum { MHL_DST_CONNECTED_RDY, MHL_DST_LINK_MODE, MHL_DST_VERSION, MHL_DST_SIZE }; /* Offset of DEVSTAT registers */ #define MHL_DST_OFFSET 0x30 #define MHL_DST_REG(name) (MHL_DST_OFFSET + MHL_DST_##name) #define MHL_DST_CONN_DCAP_RDY 0x01 #define MHL_DST_CONN_XDEVCAPP_SUPP 0x02 #define MHL_DST_CONN_POW_STAT 0x04 #define MHL_DST_CONN_PLIM_STAT_MASK 0x38 #define MHL_DST_LM_CLK_MODE_MASK 0x07 #define MHL_DST_LM_CLK_MODE_PACKED_PIXEL 0x02 #define MHL_DST_LM_CLK_MODE_NORMAL 0x03 #define MHL_DST_LM_PATH_EN_MASK 0x08 #define MHL_DST_LM_PATH_ENABLED 0x08 #define MHL_DST_LM_PATH_DISABLED 0x00 #define MHL_DST_LM_MUTED_MASK 0x10 /* Extended Device Status Registers */ enum { MHL_XDS_CURR_ECBUS_MODE, MHL_XDS_AVLINK_MODE_STATUS, MHL_XDS_AVLINK_MODE_CONTROL, MHL_XDS_MULTI_SINK_STATUS, MHL_XDS_SIZE }; /* Offset of XDEVSTAT registers */ #define MHL_XDS_OFFSET 0x90 #define MHL_XDS_REG(name) (MHL_XDS_OFFSET + MHL_XDS_##name) /* MHL_XDS_REG_CURR_ECBUS_MODE flags */ #define MHL_XDS_SLOT_MODE_8BIT 0x00 #define MHL_XDS_SLOT_MODE_6BIT 0x01 #define MHL_XDS_ECBUS_S 0x04 #define MHL_XDS_ECBUS_D 0x08 #define MHL_XDS_LINK_CLOCK_75MHZ 0x00 #define MHL_XDS_LINK_CLOCK_150MHZ 0x10 #define MHL_XDS_LINK_CLOCK_3