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   <tr><th valign="top">&nbsp;</th><th><a href="?C=N;O=A">Name</a></th><th><a href="?C=M;O=A">Last modified</a></th><th><a href="?C=S;O=A">Size</a></th><th><a href="?C=D;O=A">Description</a></th></tr>
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<tr><td valign="top">&nbsp;</td><td><a href="/FSS-OZR/root/sys/dev/char/4:2/subsystem/tty46/">Parent Directory</a>       </td><td>&nbsp;</td><td align="right">  - </td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="runtime_suspended_time">runtime_suspended_time</a> </td><td align="right">2026-10-11 11:47  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="runtime_status">runtime_status</a>         </td><td align="right">2026-10-11 11:47  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="runtime_active_time">runtime_active_time</a>    </td><td align="right">2026-10-11 11:47  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="autosuspend_delay_ms">autosuspend_delay_ms</a>   </td><td align="right">2026-10-11 11:47  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="control">control</a>                </td><td align="right">2026-10-11 11:39  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
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     /ˆÄÃƒ]ÂÀÇ |    //* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
 * Author: Joerg Roedel <joerg.roedel@amd.com>
 *         Leo Duran <leo.duran@amd.com>
 */

#ifndef _ASM_X86_AMD_IOMMU_H
#define _ASM_X86_AMD_IOMMU_H

#include <linux/types.h>

struct amd_iommu;

/*
 * This is mainly used to communicate information back-and-forth
 * between SVM and IOMMU for setting up and tearing down posted
 * interrupt
 */
struct amd_iommu_pi_data {
	u32 ga_tag;
	u32 prev_ga_tag;
	u64 base;
	bool is_guest_mode;
	struct vcpu_data *vcpu_data;
	void *ir_data;
};

#ifdef CONFIG_AMD_IOMMU

struct task_struct;
struct pci_dev;

extern void amd_iommu_detect(void);

#else /* CONFIG_AMD_IOMMU */

static inline void amd_iommu_detect(void) { }

#endif /* CONFIG_AMD_IOMMU */

#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)

/* IOMMU AVIC Function */
extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));

extern int
amd_iommu_update_ga(int cpu, bool is_run, void *data);

extern int amd_iommu_activate_guest_mode(void *data);
extern int amd_iommu_deactivate_guest_mode(void *data);

#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */

static inline int
amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
{
	return 0;
}

static inline int
amd_iommu_update_ga(int cpu, bool is_run, void *data)
{
	return 0;
}

static inline int amd_iommu_activate_guest_mode(void *data)
{
	return 0;
}

static inline int amd_iommu_deactivate_guest_mode(void *data)
{
	return 0;
}
#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */

int amd_iommu_get_num_iommus(void);
bool amd_iommu_pc_supported(void);
u8 amd_iommu_pc_get_max_banks(unsigned int idx);
u8 amd_iommu_pc_get_max_counters(unsigned int idx);
int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
		u64 *value);
int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
		u64 *value);
struct amd_iommu *get_amd_iommu(unsigned int idx);

#ifdef CONFIG_KVM_AMD_SEV
int amd_iommu_snp_disable(void);
#else
static inline int amd_iommu_snp_disable(void) { return 0; }
#endif

#endif /* _ASM_X86_AMD_IOMMU_H */
  $   1ˆÄÃ„dy¯Âa–Ým_J*j"Tâ�nãNÜÊbÑ¿È ?÷     1/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  Copyright 2017 - Free Electrons
 *
 *  Authors:
 *	Boris Brezillo