MAJOR=203
MINOR=3
DEVNAME=cpu/3/cpuid
     ˆÂÅ539_†I|¥�+¿Ä     /* SPDX-License-Identifier: GPL-2.0+ */

#ifndef __DT_BINDINGS_RESET_BCM6318_H
#define __DT_BINDINGS_RESET_BCM6318_H

#define BCM6318_RST_SPI		0
#define BCM6318_RST_EPHY	1
#define BCM6318_RST_SAR		2
#define BCM6318_RST_ENETSW	3
#define BCM6318_RST_USBD	4
#define BCM6318_RST_USBH	5
#define BCM6318_RST_PCIE_CORE	6
#define BCM6318_RST_PCIE	7
#define BCM6318_RST_PCIE_EXT	8
#define BCM6318_RST_PCIE_HARD	9
#define BCM6318_RST_ADSL	10
#define BCM6318_RST_PHYMIPS	11
#define BCM6318_RST_HOSTMIPS	12

#endif /* __DT_BINDINGS_RESET_BCM6318_H */
  
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     ˆÃÆƒy÷Þ¾¿Ä #&    /* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: James Liao <jamesjj.liao@mediatek.com>
 */

#ifndef _DT_BINDINGS_CLK_MT8173_H
#define _DT_BINDINGS_CLK_MT8173_H

/* TOPCKGEN */

#define CLK_TOP_CLKPH_MCK_O		1
#define CLK_TOP_USB_SYSPLL_125M		3
#de