PNP0b00
      ˆl–ßi~”Je¶…8 �q¦î	•1hßÁ0ÃÅ     ˆÂÁ„\_ÀÃÅ -T    /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Microsemi Ocelot Switch driver
 *
 * Copyright (c) 2017 Microsemi Corporation
 */

#ifndef _MSCC_OCELOT_DEV_H_
#define _MSCC_OCELOT_DEV_H_

#define DEV_CLOCK_CFG_MAC_TX_RST                          BIT(7)
#define DEV_CLOCK_CFG_MAC_RX_RST                          BIT(6)
#define DEV_CLOCK_CFG_PCS_TX_RST                          BIT(5)
#define DEV_CLOCK_CFG_PCS_RX_RST                          BIT(4)
#define DEV_CLOCK_CFG_PORT_RST                            BIT(3)
#define DEV_CLOCK_CFG_PHY_RST                             BIT(2)
#define DEV_CLOCK_CFG_LINK_SPEED(x)                       ((x) & GENMASK(1, 0))
#define DEV_CLOCK_CFG_LINK_SPEED_M                        GENMASK(1, 0)

#define DEV_PORT_MISC_FWD_ERROR_ENA                       BIT(4)
#define DEV_PORT_MISC_FWD_PAUSE_ENA                       BIT(3)
#define DEV_PORT_MISC_FWD_CTRL_ENA                        BIT(2)
#define DEV_PORT_MISC_DEV_LOOP_ENA                        BIT(1)
#define DEV_PORT_MISC_HDX_FAST_DIS                        BIT(0)

#define DEV_EEE_CFG_EEE_ENA                               BIT(22)
#define DEV_EEE_CFG_EEE_TIMER_AGE(x)                      (((x) << 15) & GENMASK(21, 15))
#define DEV_EEE_CFG_EEE_TIMER_AGE_M                       GENMASK(21, 15)
#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x)                    (((x) & GENMASK(21, 15)) >> 15)
#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x)                   (((x) << 8) & GENMASK(14, 8))
#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M                    GENMASK(14, 8)
#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x)                 (((x) & GENMASK(14, 8)) >> 8)
#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x)                  (((x) << 1) & GENMASK(7, 1))
#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M                   GENMASK(7, 1)
#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x)                (((x) & GENMASK(7, 1)) >> 1)
#define DEV_EEE_CFG_PORT_LPI                              BIT(0)

#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x)        (((x) << 4) & GENMASK(11, 4))
#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M         GENMASK(11, 4)
#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x)      (((x) & GENMASK(11, 4)) >> 4)
#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x)      ((x) & GENMASK(3, 0))
#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M       GENMASK(3, 0)

#define DEV_MAC_ENA_CFG_RX_ENA                            BIT(4)
#define DEV_MAC_ENA_CFG_TX_ENA                            BIT(0)

#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA                 BIT(8)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA                    BIT(4)
#define DEV_MAC_MODE_CFG_FDX_ENA                          BIT(0)

#define DEV_MAC_TAGS_CFG_TAG_ID(x)                        (((x) << 16) & GENMASK(31, 16))
#define DEV_MAC_TAGS_CFG_TAG_ID_M                         GENMASK(31, 16)
#define DEV_MAC_TAGS_CFG_TAG_ID_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA                 BIT(2)
#define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA                 BIT(1)
#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA                     BIT(0)

#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA                  BIT(0)

#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK             BIT(17)
#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG                    BIT(16)
#define DEV_MAC_IFG_CFG_TX_IFG(x)                         (((x) << 8) & GENMASK(12, 8))
#define DEV_MAC_IFG_CFG_TX_IFG_M                          GENMASK(12, 8)
#define DEV_MAC_IFG_CFG_TX_IFG_X(x)                       (((x) & GENMASK(12, 8)) >> 8)
#define DEV_MAC_IFG_CFG_RX_IFG2(x)                        (((x) << 4) & GENMASK(7, 4))
#define DEV_MAC_IFG_CFG_RX_IFG2_M                         GENMASK(7, 4)
#define DEV_MAC_IFG_CFG_RX_IFG2_X(x)                      (((x) & GENMASK(7, 4)) >> 4)
#define DEV_MAC_IFG_CFG_RX_IFG1(x)                        ((x) & GENMASK(3, 0))
#define DEV_MAC_IFG_CFG_RX_IFG1_M                         GENMASK(3, 0)

#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC        