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Index of /FSS-OZR/root/usr/src/kernels/5.14.0-687.26.1.el9_8.x86_64/tools/gpio
Index of /FSS-OZR/root/usr/src/kernels/5.14.0-687.26.1.el9_8.x86_64/tools/gpio
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„ià6ÿÎa–Ým_J*j"Tâ€zà¸&”Å£Í ?÷ k/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* ATI Mach64 Register Definitions
*
* Copyright (C) 1997 Michael AK Tesch
* written with much help from Jon Howell
*
* Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
*/
/*
* most of the rest of this file comes from ATI sample code
*/
#ifndef REGMACH64_H
#define REGMACH64_H
/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
/* Accelerator CRTC */
#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
#define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
#define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
#define CRTC_H_SYNC_STRT 0x0004
#define CRTC2_H_SYNC_STRT 0x0004
#define CRTC_H_SYNC_DLY 0x0005
#define CRTC2_H_SYNC_DLY 0x0005
#define CRTC_H_SYNC_WID 0x0006
#define CRTC2_H_SYNC_WID 0x0006
#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
#define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
#define CRTC_V_TOTAL 0x0008
#define CRTC2_V_TOTAL 0x0008
#define CRTC_V_DISP 0x000A
#define CRTC2_V_DISP 0x000A
#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
#define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
#define CRTC_V_SYNC_STRT 0x000C
#define CRTC2_V_SYNC_STRT 0x000C
#define CRTC_V_SYNC_WID 0x000E
#define CRTC2_V_SYNC_WID 0x000E
#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
#define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
#define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */
#define CRTC_OFFSET 0x0014
#define CRTC_PITCH 0x0016
#define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */
#define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */
#define CRTC_PIX_WIDTH 0x001D
#define CRTC_FIFO 0x001E
#define CRTC_EXT_DISP 0x001F
/* Memory Buffer Control */
#define DSP_CONFIG 0x0020 /* Dword offset 0_08 */
#define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */
#define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */
#define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */
#define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */
#define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */
#define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */
/* Accelerator CRTC */
#define CRT_TRAP 0x0038 /* Dword offset 0_0E */
#define I2C_CNTL_0 0x003C /* Dword offset 0_0F */
#define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */
/* Overscan */
#define OVR_CLR 0x0040 /* Dword offset 0_10 */
#define OVR2_CLR 0x0040 /* Dword offset 0_10 */
#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
#define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
#define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
/* Memory Buffer Control */
#define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */
#define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */
#define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */