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Index of /FSS-OZR/root/proc/687/task
Index of /FSS-OZR/root/proc/687/task
* l4(
( fB-
}C_I|+ $ /* SPDX-License-Identifier: GPL-2.0 */
/*
* OMAP Smartreflex Defines and Routines
*
* Author: Thara Gopinath
*
* Copyright (C) 2010 Texas Instruments, Inc.
* Thara Gopinath
*
* Copyright (C) 2008 Nokia Corporation
* Kalle Jokiniemi
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M
*/
#ifndef __POWER_SMARTREFLEX_H
#define __POWER_SMARTREFLEX_H
#include
#include
#include
#include
/*
* Different Smartreflex IPs version. The v1 is the 65nm version used in
* OMAP3430. The v2 is the update for the 45nm version of the IP
* used in OMAP3630 and OMAP4430
*/
#define SR_TYPE_V1 1
#define SR_TYPE_V2 2
/* SMART REFLEX REG ADDRESS OFFSET */
#define SRCONFIG 0x00
#define SRSTATUS 0x04
#define SENVAL 0x08
#define SENMIN 0x0C
#define SENMAX 0x10
#define SENAVG 0x14
#define AVGWEIGHT 0x18
#define NVALUERECIPROCAL 0x1c
#define SENERROR_V1 0x20
#define ERRCONFIG_V1 0x24
#define IRQ_EOI 0x20
#define IRQSTATUS_RAW 0x24
#define IRQSTATUS 0x28
#define IRQENABLE_SET 0x2C
#define IRQENABLE_CLR 0x30
#define SENERROR_V2 0x34
#define ERRCONFIG_V2 0x38
/* Bit/Shift Positions */
/* SRCONFIG */
#define SRCONFIG_ACCUMDATA_SHIFT 22
#define SRCONFIG_SRCLKLENGTH_SHIFT 12
#define SRCONFIG_SENNENABLE_V1_SHIFT 5
#define SRCONFIG_SENPENABLE_V1_SHIFT 3
#define SRCONFIG_SENNENABLE_V2_SHIFT 1
#define SRCONFIG_SENPENABLE_V2_SHIFT 0
#define SRCONFIG_CLKCTRL_SHIFT 0
#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
#define SRCONFIG_SRENABLE BIT(11)
#define SRCONFIG_SENENABLE BIT(10)
#define SRCONFIG_ERRGEN_EN BIT(9)
#define SRCONFIG_MINMAXAVG_EN BIT(8)
#define SRCONFIG_DELAYCTRL BIT(2)
/* AVGWEIGHT */
#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
/* NVALUERECIPROCAL */
#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
#define NVALUERECIPROCAL_RNSENP_SHIFT 8
#define NVALUERECIPROCAL_RNSENN_SHIFT 0
/* ERRCONFIG */
#define ERRCONFIG_ERRWEIGHT_SHIFT 16
#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
#define SR_ERRWEIGHT_MASK (0x07 << 16)
#define SR_ERRMAXLIMIT_MASK (0xff << 8)
#define SR_ERRMINLIMIT_MASK (0xff << 0)
#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
#define ERRCONFIG_MCUACCUMINTEN BIT(29)
#define ERRCONFIG_MCUACCUMINTST BIT(28)
#define ERRCONFIG_MCUVALIDINTEN BIT(27)
#define ERRCONFIG_MCUVALIDINTST BIT(26)
#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
#define ERRCONFIG_MCUBOUNDINTST BIT(24)
#define ERRCONFIG_MCUDISACKINTEN BIT(23)
#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
#define ERRCONFIG_MCUDISACKINTST BIT(22)
#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
ERRCONFIG_MCUACCUMINTST | \
ERRCONFIG_MCUVALIDINTST | \
ERRCONFIG_MCUBOUNDINTST | \
ERRCONFIG_MCUDISACKINTST)
/* IRQSTATUS */
#define IRQSTATUS_MCUACCUMINT BIT(3)
#define IRQSTATUS_MCVALIDINT BIT(2)
#define IRQSTATUS_MCBOUNDSINT BIT(1)
#defi