1 ÿFile not found. ! ɿ{! Index of /anon_sym/anon/sys/class/misc/fuse/power

Index of /anon_sym/anon/sys/class/misc/fuse/power

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 autosuspend_delay_ms 2026-10-12 09:30 4.0K 
 control 2026-10-12 09:30 4.0K 
 runtime_active_time 2026-10-12 09:30 4.0K 
 runtime_status 2026-10-12 09:30 4.0K 
 runtime_suspended_time 2026-10-12 09:30 4.0K 
# ɿ# Index of /configAHR/Jump/0-coastlinecompg/FSS-OZR/root/usr/lib/firmware/qcom/x1p42100

Index of /configAHR/Jump/0-coastlinecompg/FSS-OZR/root/usr/lib/firmware/qcom/x1p42100

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 gen71500_zap.mbn.xz 2026-05-19 08:36 2.0K 
% mĿ %/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2010 Google, Inc * Copyright (c) 2014 NVIDIA Corporation * * Author: * Colin Cross */ #ifndef __SOC_TEGRA_PMC_H__ #define __SOC_TEGRA_PMC_H__ #include #include struct clk; struct reset_control; bool tegra_pmc_cpu_is_powered(unsigned int cpuid); int tegra_pmc_cpu_power_on(unsigned int cpuid); int tegra_pmc_cpu_remove_clamping(unsigned int cpuid); /* * powergate and I/O rail APIs */ #define TEGRA_POWERGATE_CPU 0 #define TEGRA_POWERGATE_3D 1 #define TEGRA_POWERGATE_VENC 2 #define TEGRA_POWERGATE_PCIE 3 #define TEGRA_POWERGATE_VDEC 4 #define TEGRA_POWERGATE_L2 5 #define TEGRA_POWERGATE_MPE 6 #define TEGRA_POWERGATE_HEG 7 #define TEGRA_POWERGATE_SATA 8 #define TEGRA_POWERGATE_CPU1 9 #define TEGRA_POWERGATE_CPU2 10 #define TEGRA_POWERGATE_CPU3 11 #define TEGRA_POWERGATE_CELP 12 #define TEGRA_POWERGATE_3D1 13 #define TEGRA_POWERGATE_CPU0 14 #define TEGRA_POWERGATE_C0NC 15 #define TEGRA_POWERGATE_C1NC 16 #define TEGRA_POWERGATE_SOR 17 #define TEGRA_POWERGATE_DIS 18 #define TEGRA_POWERGATE_DISB 19 #define TEGRA_POWERGATE_XUSBA 20 #define TEGRA_POWERGATE_XUSBB 21 #define TEGRA_POWERGATE_XUSBC 22 #define TEGRA_POWERGATE_VIC 23 #define TEGRA_PO