input:b0003v0627p0001e0111-e0,1,4,11,14,k71,72,73,74,75,77,79,7A,7B,7C,7D,7E,7F,80,81,82,83,84,85,86,87,88,89,8A,8C,8E,96,98,9E,9F,A1,A3,A4,A5,A6,AD,B0,B1,B2,B3,B4,B7,B8,B9,BA,BB,BC,BD,BE,BF,C0,C1,C2,F0,ram4,l0,1,2,3,4,sfw  ˆÂÅ 651Á¾Ã‹ /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause */ /* * Definitions for virtio-pmem devices. * * Copyright (C) 2019 Red Hat, Inc. * * Author(s): Pankaj Gupta */ #ifndef _UAPI_LINUX_VIRTIO_PMEM_H #define _UAPI_LINUX_VIRTIO_PMEM_H #include #include #include struct virtio_pmem_config { __le64 start; __le64 size; }; #define VIRTIO_PMEM_REQ_TYPE_FLUSH 0 struct virtio_pmem_resp { /* Host return status corresponding to flush request */ __le32 ret; }; struct virtio_pmem_req { /* command type */ __le32 type; }; #endif  ˆÂÅ 0¾Ã"ˆl–Ým_J*j"Tâ€À·pO)‹FÿÆ ƒh¹¿Ä10 ˆ ƒ€/_•I|¥‰ÓMdœv ©ƒ&íK<óo¬ÀŲ Index of /FSS-OZR/root/lib/modules/5.14.0-687.31.1.el9_8.x86_64/source/security/lockdown

Index of /FSS-OZR/root/lib/modules/5.14.0-687.31.1.el9_8.x86_64/source/security/lockdown

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 Kconfig 2026-08-01 06:03 2.0K 
 Makefile 2026-08-01 06:03 50  
ˆÄÇ ƒu·]ÃÀÅ™// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2001-2002 by David Brownell */ #ifndef __LINUX_USB_EHCI_DEF_H #define __LINUX_USB_EHCI_DEF_H #include /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ struct ehci_caps { /* these fields are specified as 8 and 16 bit registers, * but some hosts can't perform 8 or 16 bit PCI accesses. * some hosts treat caplength and hciversion as parts of a 32-bit * register, others treat them as two separate registers, this * affects the memory map for big endian controllers. */ u32 hc_capbase; #define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ (ehci_big_endian_capbase(ehci) ? 24 : 0))) #define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ (ehci_big_endian_capbase(ehci) ? 0 : 16))) u32 hcs_params; /* HCSPARAMS - offset 0x4 */ #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ #define HCS_N_PORTS_MAX 15 /* N_PORTS valid 0x1-0xF */ u32 hcc_params; /* HCCPARAMS - offset 0x8 */ /* EHCI 1.1 addendum */ #define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19)) #define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18)) #define HCC_LPM(p) ((p)&(1 << 17)) #define HCC_HW_PREFETCH(p) ((p)&(1 << 16)) #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ #def