1f0000 0 0 0 0 +J/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2018 ROHM Semiconductors */ #ifndef __LINUX_MFD_BD70528_H__ #define __LINUX_MFD_BD70528_H__ #include #include #include #include #include enum { BD70528_BUCK1, BD70528_BUCK2, BD70528_BUCK3, BD70528_LDO1, BD70528_LDO2, BD70528_LDO3, BD70528_LED1, BD70528_LED2, }; struct bd70528_data { struct rohm_regmap_dev chip; struct mutex rtc_timer_lock; }; #define BD70528_BUCK_VOLTS 0x10 #define BD70528_LDO_VOLTS 0x20 #define BD70528_REG_BUCK1_EN 0x0F #define BD70528_REG_BUCK1_VOLT 0x15 #define BD70528_REG_BUCK2_EN 0x10 #define BD70528_REG_BUCK2_VOLT 0x16 #define BD70528_REG_BUCK3_EN 0x11 #define BD70528_REG_BUCK3_VOLT 0x17 #define BD70528_REG_LDO1_EN 0x1b #define BD70528_REG_LDO1_VOLT 0x1e #define BD70528_REG_LDO2_EN 0x1c #define BD70528_REG_LDO2_VOLT 0x1f #define BD70528_REG_LDO3_EN 0x1d #define BD70528_REG_LDO3_VOLT 0x20 #define BD70528_REG_LED_CTRL 0x2b #define BD70528_REG_LED_VOLT 0x29 #define BD70528_REG_LED_EN 0x2a /* main irq registers */ #define BD70528_REG_INT_MAIN 0x7E #define BD70528_REG_INT_MAIN_MASK 0x74 /* 'sub irq' registers */ #define BD70528_REG_INT_SHDN 0x7F #define BD70528_REG_INT_PWR_FLT 0x80 #define BD70528_REG_INT_VR_FLT 0x81 #define BD70528_REG_INT_MISC 0x82 #define BD70528_REG_INT_BAT1 0x83 #define BD70528_REG_INT_BAT2 0x84 #define BD70528_REG_INT_RTC 0x85 #define BD70528_REG_INT_GPIO 0x86 #define BD70528_REG_INT_OP_FAIL 0x87 #define BD70528_REG_INT_SHDN_MASK 0x75 #define BD70528_REG_INT_PWR_FLT_MASK 0x76 #define BD70528_REG_INT_VR_FLT_MASK 0x77 #define BD70528_REG_INT_MISC_MASK 0x78 #define BD70528_REG_INT_BAT1_MASK 0x79 #define BD70528_REG_INT_BAT2_MASK 0x7a #define BD70528_REG_INT_RTC_MASK 0x7b #define BD70528_REG_INT_GPIO_MASK 0x7c #define BD70528_REG_INT_OP_FAIL_MASK 0x7d /* Reset related 'magic' registers */ #define BD70528_REG_SHIPMODE 0x03 #define BD70528_REG_HWRESET 0x04 #define BD70528_REG_WARMRESET 0x05 #define BD70528_REG_STANDBY 0x06 /* GPIO registers */ #define BD70528_REG_GPIO_STATE 0x8F #define BD70528_REG_GPIO1_IN 0x4d #define BD70528_REG_GPIO2_IN 0x4f #define BD70528_REG_GPIO3_IN 0x51 #define BD70528_REG_GPIO4_IN 0x53 #define BD70528_REG_GPIO1_OUT 0x4e #define BD70528_REG_GPIO2_OUT 0x50 #define BD70528_REG_GPIO3_OUT 0x52 #define BD70528_REG_GPIO4_OUT 0x54 /* RTC */ #define BD70528_REG_RTC_COUNT_H 0x2d #define BD70528_REG_RTC_COUNT_L 0x2e #define BD70528_REG_RTC_SEC 0x2f #define BD70528_REG_RTC_MINUTE 0x30 #define BD70528_REG_RTC_HOUR 0x31 #define BD70528_REG_RTC_WEEK 0x32 #define BD70528_REG_RTC_DAY 0x33 #define BD70528_REG_RTC_MONTH 0x34 #define BD70528_REG_RTC_YEAR 0x35 #define BD70528_REG_RTC_ALM_SEC 0x36 #define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC #define BD70528_REG_RTC_ALM_MINUTE 0x37 #define BD70528_REG_RTC_ALM_HOUR 0x38 #define BD70528_REG_RTC_ALM_WEEK 0x39 #define BD70528_REG_RTC_ALM_DAY 0x3a #define BD70528_REG_RTC_ALM_MONTH 0x3b #define BD70528_REG_RTC_ALM_YEAR 0x3c #define BD70528_REG_RTC_ALM_MASK 0x3d #define BD70528_REG_RTC_ALM_REPEAT 0x3e #define BD70528_REG_RTC_START BD70528_REG_RTC_SEC #define BD70528_REG_RTC_WAKE_SEC 0x43 #define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC #define BD70528_REG_RTC_WAKE_MIN 0x44 #define BD70528_REG_RTC_WAKE_HOUR 0x45 #define BD70528_REG_RTC_WAKE_CTRL 0x46 #define BD70528_REG_ELAPSED_TIMER_EN 0x42 #define BD70528_REG_WAKE_EN 0x46 /* WDT registers */ #define BD70528_REG_WDT_CTRL 0x4A #define BD70528_REG_WDT_HOUR 0x49 #define BD70528_REG_WDT_MINUTE 0x48 #define BD70528_REG_WDT_SEC 0x47 /* Charger / Battery */ #define BD70528_REG_CHG_CURR_STAT 0x59 #define BD70528_REG_CHG_BAT_STAT 0x57 #define BD70528_REG_CHG_BAT_TEMP 0x58 #define BD70528_REG_CHG_IN_STAT 0x56 #define BD70528_REG_CHG_DCIN_ILIM 0x5d #define BD70528_REG_CHG_CHG_CURR_WARM 0x61 #define BD70528_REG_CHG_CHG_CURR_COLD 0x62 /* Masks for main IRQ register bits */ enum { BD70528_INT_SHDN, #define BD70528_INT_SHDN_MASK BIT(BD70528_INT_