MAJOR=10 MINOR=229 DEVNAME=fuse  926_I|Mdv &K Index of /anon_sym/anon/usr/share/vim/vim82/lang/fi

Index of /anon_sym/anon/usr/share/vim/vim82/lang/fi

 NameLast modifiedSizeDescription
 Parent Directory   -  
 LC_MESSAGES/ 2026-07-31 07:46 -  
*l4( (  fB- x/_I|+/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for binding nvidia,tegra114-car. * * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB * registers. These IDs often match those in the CAR's RST_DEVICES registers, * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In * this case, those clocks are assigned IDs above 160 in order to highlight * this issue. Implementations that interpret these clock IDs as bit values * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to * explicitly handle these special cases. * * The balance of the clocks controlled by the CAR are assigned IDs of 160 and * above. */ #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H /* 0 */ /* 1 */ /* 2 */ /* 3 */ #define TEGRA114_CLK_RTC 4 #define TEGRA114_CLK_TIMER 5 #define TEGRA114_CLK_UARTA 6 /* 7 (register bit affects uartb and vfir) */ /* 8 */ #define TEGRA114_CLK_SDMMC2 9 /* 10 (register bit affects spdif_in and spdif_out) */ #define TEGRA114_CLK_I2S1 11 #define TEGRA114_CLK_I2C1 12 #define TEGRA114_CLK_NDFLASH 13 #define TEGRA114_CLK_SDMMC1 14 #define TEGRA114_CLK_SDMMC4 15 /* 16 */ #define TEGRA114_CLK_PWM 17 #define TEGRA114_CLK_I2S2 18 #define TEGRA114_CLK_EPP 19 /* 20 (register bit affects vi and vi_sensor) */ #define TEGRA114_CLK_GR2D 21 #define TEGRA114_CLK_USBD 22 #define TEGRA114_CLK_ISP 23 #define TEGRA114_CLK_GR3D 24 /* 25 */ #define TEGRA114_CLK_DISP2 26 #define TEGRA114_CLK_DISP1 27 #define TEGRA114_CLK_HOST1X 28 #define TEGRA114_CLK_VCP 29 #define TEGRA114_CLK_I2S0 30 /* 31 */ #define TEGRA114_CLK_MC 32 /* 33 */ #define TEGRA114_CLK_APBDMA 34 /* 35 */ #define TEGRA114_CLK_KBC 36 /* 37 */ /* 38 */ /* 39 (register bit affects fuse and fuse_burn) */ #define TEGRA114_CLK_KFUSE 40 #define TEGRA114_CLK_SBC1 41 #define TEGRA114_CLK_NOR 42 /* 43 */ #define TEGRA114_CLK_SBC2 44 /* 45 */ #define TEGRA114_CLK_SBC3 46 #define TEGRA114_CLK_I2C5 47 #define TEGRA114_CLK_DSIA 48 /* 49 */ #define TEGRA114_CLK_MIPI 50 #define TEGRA114_CLK_HDMI 51 #define TEGRA114_CLK_CSI 52 /* 53 */ #define TEGRA114_CLK_I2C2 54 #define TEGRA114_CLK_UARTC 55 #define TEGRA114_CLK_MIPI_CAL 56 #define TEGRA114_CLK_EMC 57 #define TEGRA114_CLK_USB2 58 #define TEGRA114_CLK_USB3 59 /* 60 */ #define TEGRA114_CLK_VDE 61 #define TEGRA114_CLK_BSEA 62 #define TEGRA114_CLK_BSEV 63 /* 64 */ #define TEGRA114_CLK_UARTD 65 /* 66 */ #define TEGRA114_CLK_I2C3 67 #define TEGRA114_CLK_SBC4 68 #define TEGRA114_CLK_SDMMC3 69 /* 70 */ #define TEGRA114_CLK_OWR 71 /* 72 */ #define TEGRA114_CLK_CSITE 73 /* 74 */ /* 75 */ #define TEGRA114_CLK_LA 76 #define TEGRA114_CLK_TRACE 77 #define TEGRA114_CLK_SOC_THERM 78 #define TEGRA114_CLK_DTV 79 #define TEGRA114_CLK_NDSPEED 80 #define TEGRA114_CLK_I2CSLOW 81 #define TEGRA114_CLK_DSIB 82 #define TEGRA114_CLK_TSEC 83 /* 84 */ /* 85 */ /* 86 */ /* 87 */ /* 88 */ #define TEGRA114_CLK_XUSB_HOST 89 /* 90 */ #define TEGRA114_CLK_MSENC 91 #define TEGRA114_CLK_CSUS 92 /* 93 */