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B; A/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2014 Ulrich Hecht
*/
#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
#define __DT_BINDINGS_CLOCK_R8A73A4_H__
/* CPG */
#define R8A73A4_CLK_MAIN 0
#define R8A73A4_CLK_PLL0 1
#define R8A73A4_CLK_PLL1 2
#define R8A73A4_CLK_PLL2 3
#define R8A73A4_CLK_PLL2S 4
#define R8A73A4_CLK_PLL2H 5
#define R8A73A4_CLK_Z 6
#define R8A73A4_CLK_Z2 7
#define R8A73A4_CLK_I 8
#define R8A73A4_CLK_M3 9
#define R8A73A4_CLK_B 10
#define R8A73A4_CLK_M1 11
#define R8A73A4_CLK_M2 12
#define R8A73A4_CLK_ZX 13
#define R8A73A4_CLK_ZS 14
#define R8A73A4_CLK_HP 15
/* MSTP2 */
#define R8A73A4_CLK_DMAC 18
#define R8A73A4_CLK_SCIFB3 17
#define R8A73A4_CLK_SCIFB2 16
#define R8A73A4_CLK_SCIFB1 7
#define R8A73A4_CLK_SCIFB0 6
#define R8A73A4_CLK_SCIFA0 4
#define R8A73A4_CLK_SCIFA1 3
/* MSTP3 */
#define R8A73A4_CLK_CMT1 29
#define R8A73A4_CLK_IIC1 23
#define R8A73A4_CLK_IIC0 18
#define R8A73A4_CLK_IIC7 17
#define R8A73A4_CLK_IIC6 16
#define R8A73A4_CLK_MMCIF0 15
#define R8A73A4_CLK_SDHI0 14
#define R8A73A4_CLK_SDHI1 13
#define R8A73A4_CLK_SDHI2 12
#define R8A73A4_CLK_MMCIF1 5
#define R8A73A4_CLK_IIC2 0
/* MSTP4 */
#define R8A73A4_CLK_IIC3 11
#define R8A73A4_CLK_IIC4 10
#define R8A73A4_CLK_IIC5 9
#define R8A73A4_CLK_INTC_SYS 8
#define R8A73A4_CLK_IRQC 7
/* MSTP5 */
#define R8A73A4_CLK_THERMAL 22
#define R8A73A4_CLK_IIC8 15
#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */
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Index of /anon_sym/anon/sys/dev/char/4:2/subsystem/tty6
Index of /anon_sym/anon/sys/dev/char/4:2/subsystem/tty6
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0 K
h; K/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2023 Intel Corporation. */
#ifndef _LINUX_CXL_EVENT_H
#define _LINUX_CXL_EVENT_H
#include
#include
#include
/*
* Common Event Record Format
* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
*/
struct cxl_event_record_hdr {
u8 length;
u8 flags[3];
__le16 handle;
__le16 related_handle;
__le64 timestamp;
u8 maint_op_class;
u8 maint_op_sub_class;
u8 reserved[14];
} __packed;
struct cxl_event_media_hdr {
struct cxl_event_record_hdr hdr;
__le64 phys_addr;
u8 descriptor;
u8 type;
u8 transaction_type;
/*
* The meaning of Validity Flags from bit 2 is
* different across DRAM and General Media records
*/
u8 validity_flags[2];
u8 channel;
u8 rank;
} __packed;
#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
struct cxl_event_generic {
struct cxl_event_record_hdr hdr;
u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
} __packed;
/*
* General Media Event Record
* CXL rev 3.1 Section 8.2.9.2.1.1; Table