1843200 *l4( (  fB-  _I|+ f/* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2014 Renesas Solutions Corp. * Copyright (C) 2014 Wolfram Sang, Sang Engineering */ #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ #define __DT_BINDINGS_CLOCK_R7S72100_H__ #define R7S72100_CLK_PLL 0 #define R7S72100_CLK_I 1 #define R7S72100_CLK_G 2 /* MSTP2 */ #define R7S72100_CLK_CORESIGHT 0 /* MSTP3 */ #define R7S72100_CLK_IEBUS 7 #define R7S72100_CLK_IRDA 6 #define R7S72100_CLK_LIN0 5 #define R7S72100_CLK_LIN1 4 #define R7S72100_CLK_MTU2 3 #define R7S72100_CLK_CAN 2 #define R7S72100_CLK_ADCPWR 1 #define R7S72100_CLK_PWM 0 /* MSTP4 */ #define R7S72100_CLK_SCIF0 7 #define R7S72100_CLK_SCIF1 6 #define R7S72100_CLK_SCIF2 5 #define R7S72100_CLK_SCIF3 4 #define R7S72100_CLK_SCIF4 3 #define R7S72100_CLK_SCIF5 2 #define R7S72100_CLK_SCIF6 1 #define R7S72100_CLK_SCIF7 0 /* MSTP5 */ #define R7S72100_CLK_SCI0 7 #define R7S72100_CLK_SCI1 6 #define R7S72100_CLK_SG0 5 #define R7S72100_CLK_SG1 4 #define R7S72100_CLK_SG2 3 #define R7S72100_CLK_SG3 2 #define R7S72100_CLK_OSTM0 1 #define R7S72100_CLK_OSTM1 0 /* MSTP6 */ #define R7S72100_CLK_ADC 7 #define R7S72100_CLK_CEU 6 #define R7S72100_CLK_DOC0 5 #define R7S72100_CLK_DOC1 4 #define R7S72100_CLK_DRC0 3 #define R7S72100_CLK_DRC1 2 #define R7S72100_CLK_JCU 1 #define R7S72100_CLK_RTC 0 /* MSTP7 */ #define R7S72100_CLK_VDEC0 7 #define R7S72100_CLK_VDEC1 6 #define R7S72100_CLK_ETHER 4 #define R7S72100_CLK_NAND 3 #define R7S72100_CLK_USB0 1 #define R7S72100_CLK_USB1 0 /* MSTP8 */ #define R7S72100_CLK_IMR0 7 #define R7S72100_CLK_IMR1 6 #define R7S72100_CLK_IMRDISP 5 #define R7S72100_CLK_MMCIF 4 #define R7S72100_CLK_MLB 3 #define R7S72100_CLK_ETHAVB 2 #define R7S72100_CLK_SCUX 1 /* MSTP9 */ #define R7S72100_CLK_I2C0 7 #define R7S72100_CLK_I2C1 6 #define R7S72100_CLK_I2C2 5 #define R7S72100_CLK_I2C3 4 #define R7S72100_CLK_SPIBSC0 3 #define R7S72100_CLK_SPIBSC1 2 #define R7S72100_CLK_VDC50 1 /* and LVDS */ #define R7S72100_CLK_VDC51 0 /* MSTP10 */ #define R7S72100_CLK_SPI0 7 #define R7S72100_CLK_SPI1 6 #define R7S72100_CLK_SPI2 5 #define R7S72100_CLK_SPI3 4 #define R7S72100_CLK_SPI4 3 #define R7S72100_CLK_CDROM 2 #define R7S72100_CLK_SPDIF 1 #define R7S72100_CLK_RGPVG2 0 /* MSTP11 */ #define R7S72100_CLK_SSI0 5 #define R7S72100_CLK_SSI1 4 #define R7S72100_CLK_SSI2 3 #define R7S72100_CLK_SSI3 2 #define R7S72100_CLK_SSI4 1 #define R7S72100_CLK_SSI5 0 /* MSTP12 */ #define R7S72100_CLK_SDHI00 3 #define R7S72100_CLK_SDHI01 2 #define R7S72100_CLK_SDHI10 1 #define R7S72100_CLK_SDHI11 0 /* MSTP13 */ #define R7S72100_CLK_PIX1 2 #define R7S72100_CLK_PIX0 1 #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */  l /* SPDX-License-Identifier: GPL-2.0 * * Device Tree binding constants for Actions Semi S700 Clock Management Unit * * Copyright (c) 2014 Actions Semi Inc. * Author: David Liu * * Author: Pathiban Nallathambi * Author: Saravanan Sekar */ #ifndef __DT_BINDINGS_CLOCK_S700_H #define __DT_BINDINGS_CLOCK_S700_H #define CLK_NONE 0 /* pll clocks */ #define CLK_CORE_PLL 1 #define CLK_DEV_PLL 2 #define CLK_DDR_PLL 3 #define CLK_NAND_PLL 4 #define CLK_DISPLAY_PLL 5 #define CLK_TVOUT_PLL 6 #define CLK_CVBS_PLL 7 #define CLK_AUDIO_PLL 8 #define CLK_ETHERNET_PLL 9 /* system clock */ #define CLK_CPU 10 #define CLK_DEV 11 #define CLK_AHB 12 #define CLK_APB 13 #define CLK_DMAC 14 #define CLK_NOC0_CLK_MUX 15 #define CLK_NOC1_CLK_MUX 16 #define CLK_HP_CLK_MUX 17 #define CLK_HP_CLK_DIV 18 #define CLK_NOC1_CLK_DIV 19 #define CLK_NOC0 20 #define CLK_NOC1 21 #define CLK_SENOR_SRC 22 /* peripheral device clock */ #define CLK_GPIO 23 #define CLK_TIMER 24 #define CLK_DSI 25 #define CLK_CSI 26 #define CLK_SI 27 #define CLK_DE 28 #define CLK_HDE 29 #define CLK_VDE 30 #define CLK_VCE 31 #define CLK_NAND 32 #define CLK_SD0 33 #define CLK_SD1 34 #define CLK_SD2 35 #define CLK_UART0 36 #d