MAJOR=4 MINOR=49 DEVNAME=tty49 !ˆËÊ „™¿Å¾È0!/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ /* Copyright(c) 2015-17 Intel Corporation. */ #ifndef __SDW_REGISTERS_H #define __SDW_REGISTERS_H #include #include /* * SDW registers as defined by MIPI 1.2 Spec */ #define SDW_REGADDR GENMASK(14, 0) #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15) #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23) #define SDW_REG_NO_PAGE 0x00008000 #define SDW_REG_OPTIONAL_PAGE 0x00010000 #define SDW_REG_MAX 0x48000000 #define SDW_DPN_SIZE 0x100 #define SDW_BANK1_OFFSET 0x10 /* * DP0 Interrupt register & bits * * Spec treats Status (RO) and Clear (WC) as separate but they are same * address, so treat as same register with WC. */ /* both INT and STATUS register are same */ #define SDW_DP0_INT 0x0 #define SDW_DP0_INTMASK 0x1 #define SDW_DP0_PORTCTRL 0x2 #define SDW_DP0_BLOCKCTRL1 0x3 #define SDW_DP0_PREPARESTATUS 0x4 #define SDW_DP0_PREPARECTRL 0x5 #define SDW_DP0_INT_TEST_FAIL BIT(0) #define SDW_DP0_INT_PORT_READY BIT(1) #define SDW_DP0_INT_BRA_FAILURE BIT(2) #define SDW_DP0_SDCA_CASCADE BIT(3) /* BIT(4) not allocated in SoundWire specification 1.2 */ #define SDW_DP0_INT_IMPDEF1 BIT(5) #define SDW_DP0_INT_IMPDEF2 BIT(6) #define SDW_DP0_INT_IMPDEF3 BIT(7) #define SDW_DP0_INTERRUPTS (SDW_DP0_INT_TEST_FAIL | \ SDW_DP0_INT_PORT_READY | \ SDW_DP0_INT_BRA_FAILURE | \ SDW_DP0_INT_IMPDEF1 | \ SDW_DP0_INT_IMPDEF2 | \ SDW_DP0_INT_IMPDEF3) #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2) #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4) #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6) #define SDW_DP0_CHANNELEN 0x20 #define SDW_DP0_SAMPLECTRL1 0x22 #define SDW_DP0_SAMPLECTRL2 0x23 #define SDW_DP0_OFFSETCTRL1 0x24 #define SDW_DP0_OFFSETCTRL2 0x25 #define SDW_DP0_HCTRL 0x26 #define SDW_DP0_LANECTRL 0x28 /* Both INT and STATUS register are same */ #define SDW_SCP_INT1 0x40 #define SDW_SCP_INTMASK1 0x41 #define SDW_SCP_INT1_PARITY BIT(0) #define SDW_SCP_INT1_BUS_CLASH BIT(1) #define SDW_SCP_INT1_IMPL_DEF BIT(2) #define SDW_SCP_INT1_SCP2_CASCADE BIT(7) #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3) #define SDW_SCP_INTSTAT2 0x42 #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7) #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0) #define SDW_SCP_INTSTAT3 0x43 #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0) /* Number of interrupt status registers */ #define SDW_NUM_INT_STAT_REGISTERS 3 /* Number of interrupt clear registers */ #define SDW_NUM_INT_CLEAR_REGISTERS 1 #define SDW_SCP_CTRL 0x44 #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1) #define SDW_SCP_CTRL_FORCE_RESET BIT(7) #define SDW_SCP_STAT 0x44 #define SDW_SCP_STAT_CLK_STP_NF BIT(0) #define SDW_SCP_STAT_HPHY_NOK BIT(5) #define SDW_SCP_STAT_CURR_BANK BIT(6) #define SDW_SCP_SYSTEMCTRL 0x45 #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0) #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2) #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3) #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4) #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0 0 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2) #define SDW_SCP_DEVNUMBER 0x46 #define SDW_SCP_HIGH_PHY_CHECK 0x47 #define SDW_SCP_ADDRPAGE1 0x48 #define SDW_SCP_ADDRPAGE2 0x49 #define SDW_SCP_KEEPEREN 0x4A #define SDW_SCP_BANKDELAY 0x4B #define SDW_SCP_COMMIT 0x4C #define SDW_SCP_BUS_CLOCK_BASE 0x4D #define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0) #define SDW_SCP_BASE_CLOCK_UNKNOWN 0x0 #define SDW_SCP_BASE_CLOCK_19200000_HZ 0x1 #define SDW_SCP_BASE_CLOCK_24000000_HZ 0x2 #define SDW_SCP_BASE_CLOCK_24576000_HZ 0x3 #define SDW_SCP_BASE_CLOCK_22579200_HZ 0x4 #define SDW_SCP_BASE_CLOCK_32000000_HZ 0x5 #define SDW_SCP_BASE_CLOCK_RESERVED 0x6 #define SDW_SCP_BASE_CLOCK_IMP_DEF 0x7 /* 0x4E is not allocated in SoundWire specification 1.2 */ #define SDW_SCP_TESTMODE 0x4F #define SDW_SCP_DEVID_0 0x50 #define SDW_SCP_DEVID_1 0x51 #define SDW_SCP_DEVID_2 0x52 #define SDW_SCP_DEVID_3