PRODUCT=11/2/13/6
NAME="VirtualPS/2 VMware VMMouse"
PHYS="isa0060/serio1/input0"
PROP=1
EV=7
KEY=30000 0 0 0 0
REL=103
MODALIAS=input:b0011v0002p0013e0006-e0,1,2,k110,111,r0,1,8,amlsfw
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     !ˆÁÄƒuÇ_ÀÂÆ ÿ    !/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Andrzej Hajda <a.hajda@samsung.com>
 *
 * Device Tree binding constants for Exynos4 clock controller.
 */

#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
#define _DT_BINDINGS_CLOCK_EXYNOS_4_H

/* core clocks */
#define CLK_XXTI		1
#define CLK_XUSBXTI		2
#define CLK_FIN_PLL		3
#define CLK_FOUT_APLL		4
#define CLK_FOUT_MPLL		5
#define CLK_FOUT_EPLL		6
#define CLK_FOUT_VPLL		7
#define CLK_SCLK_APLL		8
#define CLK_SCLK_MPLL		9
#define CLK_SCLK_EPLL		10
#define CLK_SCLK_VPLL		11
#define CLK_ARM_CLK		12
#define CLK_ACLK200		13
#define CLK_ACLK100		14
#define CLK_ACLK160		15
#define CLK_ACLK133		16
#define CLK_MOUT_MPLL_USER_T	17 /* Exynos4x12 only */
#define CLK_MOUT_MPLL_USER_C	18 /* Exynos4x12 only */
#define CLK_MOUT_CORE		19
#define CLK_MOUT_APLL		20
#define CLK_SCLK_HDMIPHY	22
#define CLK_OUT_DMC		23
#define CLK_OUT_TOP		24
#define CLK_OUT_LEFTBUS		25
#define CLK_OUT_RIGHTBUS	26
#define CLK_OUT_CPU		27

/* gate for special clocks (sclk) */
#define CLK_SCLK_FIMC0		128
#define CLK_SCLK_FIMC1		129
#define CLK_SCLK_FIMC2		130
#define CLK_SCLK_FIMC3		131
#define CLK_SCLK_CAM0		132
#define CLK_SCLK_CAM1		133
#define CLK_SCLK_CSIS0		134
#define CLK_SCLK_CSIS1		135
#define CLK_SCLK_HDMI		136
#define CLK_SCLK_MIXER		137
#define CLK_SCLK_DAC		138
#define CLK_SCLK_PIXEL		139
#define CLK_SCLK_FIMD0		140
#define CLK_SCLK_MDNIE0		141 /* Exynos4412 only */
#define CLK_SCLK_MDNIE_PWM0	142
#define CLK_SCLK_MIPI0		143
#define CLK_SCLK_AUDIO0		144
#define CLK_SCLK_MMC0		145
#define CLK_SCLK_MMC1		146
#define CLK_SCLK_MMC2		147
#define CLK_SCLK_MMC3		148
#define CLK_SCLK_MMC4		149
#define CLK_SCLK_SATA		150 /* Exynos4210 only */
#define CLK_SCLK_UART0		151
#define CLK_SCLK_UART1		152
#define CLK_SCLK_UART2		153
#define CLK_SCLK_UART3		154
#define CLK_SCLK_UART4		155
#define CLK_SCLK_AUDIO1		156
#define CLK_SCLK_AUDIO2		157
#define CLK_SCLK_SPDIF		158
#define CLK_SCLK_SPI0		159
#define CLK_SCLK_SPI1		160
#define CLK_SCLK_SPI2		161
#define CLK_SCLK_SLIMBUS	162
#define CLK_SCLK_FIMD1		163 /* Exynos4210 only */
#define CLK_SCLK_MIPI1		164 /* Exynos4210 only */
#define CLK_SCLK_PCM1		165
#define CLK_SCLK_PCM2		166
#define CLK_SCLK_I2S1		167
#define CLK_SCLK_I2S2		168
#define CLK_SCLK_MIPIHSI	169 /* Exynos4412 only */
#define CLK_SCLK_MFC		170
#define CLK_SCLK_PCM0		171
#define CLK_SCLK_G3D		172
#define CLK_SCLK_PWM_ISP	173 /* Exynos4x12 only */
#define CLK_SCLK_SPI0_ISP	174 /* Exynos4x12 only */
#define CLK_SCLK_SPI1_ISP	175 /* Exynos4x12 only */
#define CLK_SCLK_UART_ISP	176 /* Exynos4x12 only */
#define CLK_SCLK_FIMG2D		177

/* gate clocks */
#define CLK_SSS			255
#define CLK_FIMC0		256
#define CLK_FIMC1		257
#define CLK_FIMC2		258
#define CLK_FIMC3		259
#define CLK_CSIS0		260
#define CLK_CSIS1		261
#define CLK_JPEG		262
#define CLK_SMMU_FIMC0		263
#define CLK_SMMU_FIMC1		264
#define CLK_SMMU_FIMC2		265
#define CLK_SMMU_FIMC3		266
#define CLK_SMMU_JPEG		267
#define CLK_VP			268
#define CLK_MIXER		269
#define CLK_TVENC		270 /* Exynos4210 only */
#define CLK_HDMI		271
#define CLK_SMMU_TV		272
#define CLK_MFC			273
#define CLK_SMMU_MFCL		274
#define CLK_SMMU_MFCR		275
#define CLK_G3D			276
#define CLK_G2D			277
#define CLK_ROTATOR		278
#define CLK_MDMA		279
#define CLK_SMMU_G2D		280
#define CLK_SMMU_ROTATOR	281
#define CLK_SMMU_MDMA		282
#define CLK_FIMD0		283
#define CLK_MIE0		284
#define CLK_MDNIE0		285 /* Exynos4412 only */
#define CLK_DSIM0		286
#define CLK_SMMU_FIMD0		287
#define CLK_FIMD1		288 /* Exynos4210 only */
#define CLK_MIE1		289 /* Exynos4210 only */
#define CLK_DSIM1		290 /* Exynos4210 only */
#define CLK_SMMU_FIMD1		291 /* Exynos4210 only */
#define CLK_PDMA0		292
#define CLK_PDMA1		293
#define CLK_PCIE_PHY		294
#define CLK_SATA_PHY		295 /* Exynos4210 o